LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 228
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LM3S600-IQN20-A0T
Manufacturer Part Number
LM3S600-IQN20-A0T
Description
Microcontroller
Manufacturer
Bookham Technology, Inc.
Datasheet
1.LM3S600-IQN20-A0T.pdf
(378 pages)
- Current page: 228 of 378
- Download datasheet (4Mb)
Universal Asynchronous Receivers/Transmitters (UARTs)
228
Bit/Field
2:0
4
3
reserved
Name
RXFE
BUSY
Type
RO
RO
RO
Reset
1
0
0
Preliminary
Description
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding register
is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is empty.
UART Busy
When this bit is 1, the UART is busy transmitting data. This bit remains
set until the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
October 01, 2007
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