LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 124
![no-image](/images/no-image-200.jpg)
LM3S600-IQN20-A0T
Manufacturer Part Number
LM3S600-IQN20-A0T
Description
Microcontroller
Manufacturer
Bookham Technology, Inc.
Datasheet
1.LM3S600-IQN20-A0T.pdf
(378 pages)
- Current page: 124 of 378
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General-Purpose Input/Outputs (GPIOs)
Table 8-3. GPIO Register Map
124
0xFDC
0xFEC
Offset
0x40C
0x41C
0x50C
0x51C
0xFD0
0xFD4
0xFD8
0xFE0
0xFE4
0xFE8
0x000
0x400
0x404
0x408
0x410
0x414
0x418
0x420
0x500
0x504
0x508
0x510
0x514
0x518
0xFF0
0xFF4
0xFF8
Name
GPIODATA
GPIODIR
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIOAFSEL
GPIODR2R
GPIODR4R
GPIODR8R
GPIOODR
GPIOPUR
GPIOPDR
GPIOSLR
GPIODEN
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
Note:
The default reset value for the GPIOAFSEL register is 0x0000.0000 for all GPIO pins, with
the exception of the five JTAG pins (PB7 and PC[3:0]). These five pins default to JTAG
functionality. Because of this, the default reset value of GPIOAFSEL for GPIO Port B is
0x0000.0080 while the default reset value for Port C is 0x0000.000F.
Type
W1C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0x0000.000D
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.00FF
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.00FF
0x0000.0000
0x0000.0000
0x0000.00FF
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0061
0x0000.0000
0x0000.0018
0x0000.0001
0x0000.00F0
0x0000.0005
Reset
-
Preliminary
Description
GPIO Data
GPIO Direction
GPIO Interrupt Sense
GPIO Interrupt Both Edges
GPIO Interrupt Event
GPIO Interrupt Mask
GPIO Raw Interrupt Status
GPIO Masked Interrupt Status
GPIO Interrupt Clear
GPIO Alternate Function Select
GPIO 2-mA Drive Select
GPIO 4-mA Drive Select
GPIO 8-mA Drive Select
GPIO Open Drain Select
GPIO Pull-Up Select
GPIO Pull-Down Select
GPIO Slew Rate Control Select
GPIO Digital Enable
GPIO Peripheral Identification 4
GPIO Peripheral Identification 5
GPIO Peripheral Identification 6
GPIO Peripheral Identification 7
GPIO Peripheral Identification 0
GPIO Peripheral Identification 1
GPIO Peripheral Identification 2
GPIO Peripheral Identification 3
GPIO PrimeCell Identification 0
GPIO PrimeCell Identification 1
GPIO PrimeCell Identification 2
October 01, 2007
page
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