PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 72

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

to the received signal amplitude, no selection of long haul or short haul mode is
necessary.
6.1.3
The FALC
up to -43 dB. The maximum reachable length with a 22 AWG twisted pair cable is
1500 m. The integrated receive equalization network recovers signals with up to -43 dB
of cable attenuation. Noise filters eliminate the higher frequency part of the received
signals. The incoming data is peak-detected and sliced to produce the digital data
stream. The slicing level is software selectable in four steps (45%, 50%, 55%, 67%). For
typical E1 applications, a level of 50% is used. The received data is then forwarded to
the clock & data recovery unit.
The receive equalizer characteristic is programmable, for example to enable the use of
non-standard cable types or to adapt to specific receive conditions.
6.1.4
Status register RES reports the current receive line attenuation in a range from 0 to -43
dB in 25 steps of approximately 1.7 dB each. The least significant 5 bits of this register
indicate the cable attenuation in dB. These 5 bits are only valid in combination with the
most significant two bits (RES.EV1/0 = 01).
6.1.5
The analog received signal on port RL1/2 is equalized and then peak-detected to
produce a digital signal. The digital received signal on port RDIP/N is directly forwarded
to the DPLL. The receive clock and data recovery extracts the route clock from the data
stream received at the RL1/2, RDIP/RDIN or ROID lines and converts the data stream
into a single-rail, unipolar bit stream. The clock and data recovery uses an internally
generated high frequency clock based on MCLK.
The recovered route clock or a de-jittered clock can be output on pin RCLK as shown in
Table
See also
Data Sheet
13.
Table 16
®
Receive Equalization Network (E1)
Receive Line Attenuation Indication (E1)
Receive Clock and Data Recovery (E1)
56 automatically recovers the signals received on pins RL1/2 in a range of
on page
79
for details of master/slave clocking.
72
Functional Description E1
Rev. 1.1, 2005-06-13
PEF 2256 H/E
FALC
®
56