PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 223

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

10.3
10.3.1
When programmed in the extended transparent mode via the MODE registers
(MODE.MDS(2:0) = 111,
FALC
framing, i.e. without
•
•
•
In order to enable fully transparent data transfer, bit MODE.HRAC (MODE2.HRAC2,
MODE3.HRAC3) has to be set.
Received data is always shifted into RFIFO (RFIFO2, RFIFO3).
Data transmission is always performed out of XFIFO (XFIFO2, XFIFO3) by shifting the
contents of XFIFO into the outgoing data stream directly. Transmission is initiated by
setting CMDR.XTF (04
first byte of the XFIFO is transmitted.
Cyclic Transmission (fully transparent)
If the extended transparent mode is selected, the FALC
transmission of the contents of the transmit FIFOs.
After having written 1 to 32 bytes to XFIFO (XFIFO2, XFIFO3), the command
XREP&XTF (CMDR = 00100100 = 24
in XFIFO to the remote end repeatedly.
Note: The cyclic transmission continues until a reset command (CMDR.SRES) is issued
10.3.2
As an option in HDLC mode the internal handling of the received and transmitted CRC
checksum can be influenced via control bits CCR2.RCRC and CCR2.XCRC (channel 2:
CCR3.RCRC2, CCR3.XCRC2, channel 3: CCR4.RCRC3, CCR4.XCRC3).
•
The received CRC checksum is always assumed to be in the 2 last bytes of a frame
(CRC-ITU), immediately preceding a closing flag. If CCR2.RCRC is set, the received
CRC checksum is written to RFIFO where it precedes the frame status byte (contents of
register RSIS). The received CRC checksum is additionally checked for correctness. If
Data Sheet
Flag insertion and deletion
CRC generation and checking
Bit stuffing
Receive Direction
®
or with resetting of CMDR.XREP, after which continuous “1”s are transmitted.
During cyclic transmission the XREP-bit has to be set with every write operation
to CMDR.
The same handling applies to CMDR2 and CMDR3 for HDLC channels 2 an 3.
56 performs fully transparent data transmission and reception without HDLC
Signaling Controller Functions
Transparent Transmission and Reception
CRC on/off Features
H
). A synchronization byte FF
MODE2.MDS2(2:0)=111,
H
) forces the FALC
223
Signaling Controller Operating Modes
H
is sent automatically before the
MODE3.MDS3(2:0)=111),
®
56 to transmit the data stored
®
56 supports the continuous
Rev. 1.1, 2005-06-13
PEF 2256 H/E
FALC
®
the
56