PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 258

PEF2256EV22NP

Manufacturer Part Number
PEF2256EV22NP
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEF2256EV22NP

Number Of Transceivers
1
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Supplier Unconfirmed
Data Sheet
Delay time T = time between beginning of time slot 0 at RDO and the
initial edge of SCLKR after SYPR goes active.
See
Receive Frame Marker Offset (PC(4:1).RPC(2:0) = 001
Offset programming of the receive frame marker which is output on
multifunction port RFM. The receive frame marker can be activated
during any bit position of the entire frame and depends on the
selected system clock rate.
Calculation of the value X of the receive offset register RC(1:0)
depends on the bit position which should be marked at marker
position MP:
0
2046
e.g: 2.048 MHz: MP = 0 to 255; up to 16.384 MHz: MP = 0 to 2047
MP
page 117
MP
2045:X = MP + 2
2047: X = MP - 2046
for further description.
258
Rev. 1.1, 2005-06-13
PEF 2256 H/E
E1 Registers
B
FALC
)
®
56

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