PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 111

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

The FALC
combinations of time slots can be programmed separately for the receive and transmit
direction if using HDLC channel 1. HDLC channel 2 and 3 support one programmable
time slot common for receive and transmit direction each.
Each HDLC controller can be used to operate on the line side (called "normal HDLC") or
on the system side (called "inverse HDLC").
6.4.7.2
The HDLC controller of channel 1 supports the signaling system #7 (SS7) which is
described in ITU-Q.703. The following description assumes, that the reader is familiar
with the SS7 protocol definition.
SS7 support must be activated by setting the MODE register. Data stored in the transmit
FIFO (XFIFO) is sent automatically. The SS7 protocol is supported by the following
hardware features in transmit direction:
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•
•
Each Signaling Unit written to the transmit FIFO (XFIFO, 2 32 bytes) is sent once or
repeatedly including flags, CRC checksum and stuffed bits. After e.g. an MSU has been
transmitted completely, the FALC
forward sequence number (FSN) and the backward sequence number (BSN) of the
previously transmitted Signaling Unit. Setting bit CCR5.AFX causes Fill In Signaling
Units (FISUs) to be sent continuously, if no HDLC or Signaling Unit (SU) is to be
transmitted from XFIFO. During update of XFIFO, automatic transmission is interrupted
and resumed after update is completed. The internally generated FISUs contain FSN
and BSN of the last transmitted Signaling Unit written to XFIFO.
Using CMDR.XREP = 1, the contents of XFIFO can be sent continuously. Clearing of
CMDR.XRES/SRES stops the automatic repetition of transmission. This function is also
available for HDLC frames, so no flag generation, CRC byte generation and bit stuffing
is necessary.
Example: After an MSU has been sent repetitively and XREP has been cleared, FISUs
are sent automatically.
6.4.7.3
The FALC
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Data Sheet
Transmission of flags at the beginning of each Signaling Unit
Bit stuffing (zero insertion)
Calculation of the CRC16 checksum:
The transmitter adds the checksum to each Signaling Unit.
The access through register XSW
The access through registers XSA(8:4), capable of storing the information for a
complete multiframe
®
®
Support of Signaling System #7
S
56 supports the S
56 offers the flexibility to insert data during certain time slots. Any
a
-Bit Access (E1)
a
-bit signaling of time slot 0 of every other frame as follows:
®
56 optionally starts sending of FISUs containing the
111
Functional Description E1
Rev. 1.1, 2005-06-13
PEF 2256 H/E
FALC
®
56