PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 179

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 46
Bit Value
G1 = 1
G2 = 1
G3 = 1
G4 = 1
G5 = 1
G6 = 1
SE = 1
FE = 1
LV = 1
SL = 1
LB = 1
U1
U2
R
NmNi
1)
7.5
The FALC
receive direction different system clocks and system pulses are necessary. The interface
to the receive system highway is realized by two data buses, one for the data RDO and
one for the signaling data RSIG. The receive highway is clocked on pin SCLKR, while
the interface to the transmit system highway is independently clocked on pin SCLKX.
The
2.048/4.096/8.192/16.384/1.544/3.088/6.192/12.352 Mbit/s for the receive and transmit
system interface is programmable by SIC1.SSC1/0, SIC2.SSC2 and SIC1.SSD1,
FMR1.SSD0. Selectable system clock and data rates and their valid combinations are
shown in the table below.
Data Sheet
according to ANSI T1.403
frequency
®
System Interface in T1/J1 Mode
56 offers a flexible feature for system designers where for transmit and
Bit Functions in Periodical Performance Report
Interpretation
Number of CRC error events = 1
1 < number of CRC error events
5 < number of CRC error events
10 < number of CRC error events
100 < number of CRC error events
Number of CRC error events
Severely errored framing event
Frame synchronization bit error event
Line code violation event
Slip event
Payload loop-back activated
Not used (default value = 0)
Not used (default value = 0)
Not used (default value = 0)
One-second report modulo 4 counter
of
these
1
working
179
1
clocks
320
1 (FE shall be 0)
5
10
100
319
1 (SE shall be 0)
Functional Description T1/J1
and
the
1)
Rev. 1.1, 2005-06-13
data
PEF 2256 H/E
FALC
rate
®
56
of