PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 406

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

DCF
IRSP
IRSC
Data Sheet
DCO-R Center- Frequency Disabled
0 =
1 =
Internal Receive System Frame Sync Pulse
0 =
1 =
Internal Receive System Clock
0 =
1 =
The DCO-R circuitry is frequency centered
- in master mode if no 1.544 or 2.048 MHz reference clock on
pin SYNC is provided or
- in slave mode if a loss-of-signal occurs in combination with no
1.544 or 2.048 MHz clock on pin SYNC or
- a gapped clock is provided on pin RCLKI and this clock is
inactive or stopped.
The center function of the DCO-R circuitry is disabled. The
generated clock (DCO-R) is frequency frozen in that moment
when no clock is available on pin SYNC or pin RCLKI. The
DCO-R circuitry starts synchronization as soon as a clock on
pins SYNC or RCLKI appears.
The frame sync pulse for the receive system interface is
sourced by SYPR (if SYPR is applied). If SYPR is not applied,
the frame sync pulse is derived from RDO output signal
internally free running).
The use of IRSP = 0 is recommended.
The frame sync pulse for the receive system interface is
internally sourced by the DCO-R circuitry. This internally
generated frame sync signal can be output (active low) on
multifunction ports RP(A to D) (RPC(2:0) = 001
Note: This is the only exception where the use of RFM and
SYPR is allowed at the same time. Because only one set of
offset registers (RC1/0) is available, programming is done by
using the SYPR calculation formula in the same way as for the
external SYPR pulse. Bit IRSC must be set for correct
operation.
The working clock for the receive system interface is sourced
by SCLKR of or in receive elastic buffer bypass mode from the
corresponding extracted receive clock RCLK.
The working clock for the receive system interface is sourced
internally by DCO-R or in bypass mode by the extracted receive
clock. SCLKR is ignored.
406
Rev. 1.1, 2005-06-13
T1/J1 Registers
PEF 2256 H/E
B
).
FALC
®
56