PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 291

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Command Register 2 (Write)
Value after reset: 00
CMDR2
RSUC
Command Register 3 (Write)
Value after reset: 00
CMDR3
RMC2
XREP2
XHF2
Data Sheet
RMC2
7
Reset Signaling Unit Counter
After setting this bit the SS7 signaling unit counter and error counter
are reset.The bit is cleared automatically after execution.
Note: The maximum time between writing to the CMDR2 register
Receive Message Complete - HDLC Channel 2
Confirmation from CPU to FALC
has been fetched following an RPF2 or RME2 interrupt, thus the
occupied space in the RFIFO2 can be released.
Transmission Repeat - HDLC Channel 2
If XREP2 is set together with XTF2 (write 24H to CMDR3), the FALC
repeatedly transmits the contents of the XFIFO2 (1 to 32 bytes)
without HDLC framing fully transparently, i.e. without flag, CRC.
The cyclic transmission is stopped with an SRES2 command or by
resetting XREP2.
Transmit HDLC Frame - HDLC Channel 2
After having written up to 32 bytes to the XFIFO2, this command
initiates the transmission of a HDLC frame.
H
H
and the execution of the command takes 2.5 periods of the
current system data rate. Therefore, if the CPU operates with
a very high clock rate in comparison with the FALC
it is recommended that bit SIS.CEC should be checked before
writing to the CMDR2 register to avoid any loss of commands.
XREP2
291
XHF2
®
that the current frame or data block
XTF2
RSUC
XME2
Rev. 1.1, 2005-06-13
SRES2
PEF 2256 H/E
E1 Registers
0
®
FALC
56's clock,
(x87)
(88)
®
56
®