CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 98

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

I2C Slave
14.1.1
Figure 14-2
I2C bus with a 7-bit address format. (For a more detailed
description, see the Philips Semiconductors’ I
cation, version 2.1.)
A Start condition (generated by the master) is followed by a
data byte, consisting of a 7-bit slave address (there is also a
10-bit address mode) and a Read/Write (RW) bit. The RW
bit sets the direction of data transfer. The addressed slave is
required to acknowledge (ACK) the bus by pulling the data
98
shows the basic form of data transfers on the
Basic I
START
2
C Data Transfer
Figure 14-2. Basic I
1
7-Bit Address
7
2
C™ Specifi-
R/W
2
8
C Data Transfer with 7-Bit Address Format
ACK
9
line low during the ninth bit time. If the ACK is received, the
transfer may proceed and the master can transmit or
receive an indeterminate number of bytes, depending on the
RW direction. If the slave does not respond with an ACK for
any reason, a Stop condition is generated by the master to
terminate the transfer or a Restart condition may be gener-
ated for a retry attempt.
1
8-Bit Data
7
8
PSoC CY8C20x34 TRM, Version 1.0
NACK
ACK/
9
STOP