CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 92

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Digital Clocks
13.1.3
The ability to replace the 12 MHz internal main oscillator
(IMO), as the device master system clock (SYSCLK) with an
externally supplied clock, is a feature in the PSoC mixed-
signal array (see
Pin P1[4] is the input pin for the external clock. If P1[4] is
selected as the external clock source, the drive mode of the
pin must be set to High-Z (not High-Z analog).
An external clock with a frequency between 1 MHz and 12
MHz can be supplied. The reset state of the EXTCLKEN bit
is ‘0’; therefore, the device always boots up under the con-
trol of the IMO. There is no way to start the system from a
reset state with the external clock.
When the EXTCLKEN bit is set, the external clock becomes
the source for the internal clock tree, SYSCLK, which drives
most PSoC device clocking functions. All external and inter-
nal signals, including the 1 kHz clock, are synchronized to
this clock source.
92
External Clock
IMO Trim Register
Slow IMO Option
Figure
CPU_SCR1[4]
IMO_TR[7:0]
Oscillator
Internal
(IMO)
Main
13-1).
ILO Trim Register
Low Speed
ILO_TR[7:0]
Oscillator
Figure 13-1. Overview of PSoC Clock Sources
OSC_CR2[2]
Internal
(ILO)
EXTCLK
P1[4]
(EXTCLK Input)
13.1.3.1
Switching between the IMO and the external clock may be
done in firmware at any time and is transparent to the user.
Since all PSoC device resources run on clocks derived from
or synchronized to SYSCLK, when the switch is made, ana-
log and digital functions may be momentarily interrupted.
When a switch is made from the IMO to the external clock,
the IMO may be turned off to save power. This is done by
setting the IMODIS bit and may be done immediately after
the instruction that sets the EXTCLKEN bit. However, the
IMO must not be disabled if the external clock is slower than
6 MHz. When switching back from an external clock to the
IMO, the IMODIS bit must be cleared and a firmware delay
implemented. This gives the IMO sufficient start-up time
before the EXTCLKEN bit is cleared.
Switch timing depends on whether the CPU clock divider is
set for divide by 1, or divide by 2 or greater. In the case
where the CPU clock divider is set for divide by 2 or greater,
as shown in
occurs shortly after the rising edge of SYSCLK. The
SYSCLK output is then disabled after the next falling edge
of SYSCLK, but before the next rising edge. This ensures a
Sleep Clock Divider
OSC_CR0[2:0]
OSC_CR0[4:3]
Clock Divider
Figure
Switch Operation
1
2
4
8
16
32
128
256
2
2
2
2
6
9
12
15
13-2, the setting of the EXTCLKEN bit
PSoC CY8C20x34 TRM, Version 1.0
CPUCLK
SYSCLK
SLEEP
CLK32K