CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 167
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CY8C20X34
Manufacturer Part Number
CY8C20X34
Description
Technical Reference Manual (TRM)
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY8C20X34.pdf
(218 pages)
- Current page: 167 of 218
- Download datasheet (3Mb)
20.3.27 IDX_PP
This register is used to set the effective SRAM page for indexed memory accesses in a multi-SRAM page PSoC device.
This register is only used when a device has more than one page of SRAM.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits should always be written with a value of ‘0’. For additional information, refer to the
36
Bit
0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
IDX_PP: 0,D3h
Access : POR
Bit Name
in the RAM Paging chapter .
Page Bit
Name
Indexed Memory Access Page Pointer Register
7
6
Description
Bit determines which SRAM page an indexed memory access operates on. See the
tions on page 36
0b
1b
Note A value beyond the available SRAM, for a specific PSoC device, should not be set.
SRAM Page 0
SRAM Page 1
5
for more information on when this register is active.
4
3
2
Register Definitions on page
1
0,D3h
Register Defini-
Page Bit
RW : 0
0,D3h
IDX_PP
0
167
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