CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 189

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

20.4.7
This register is used to configure various features of internal clock sources and clock nets.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved
bits should always be written with a value of ‘0’. For additional information, refer to the
Digital Clocks chapter.
Bit
6
5
4:3
2:0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
OSC_CR0: 1,E0h
Access : POR
Bit Name
Disable Buzz
No Buzz
Sleep[1:0]
CPU Speed[2:0]
Name
OSC_CR0
Oscillator Control Register 0
7
Disable Buzz
RW : 0
6
Description
Bit has lower priority than the No Buzz bit. Therefore if No Buzz = 1, the Disable Buzz bit has not
effect.
0
1
0
1
Sleep Interval
00b
01b
10b
11b
Bits set the CPU clock speed, based on the system clock (SYSCLK). SYSTOLE is 12 MHz by default,
but it can optionally be set to 6 MHz or be driven from an external clock.
000b
001b
010b
011b
100b
101b
110b
111b
No effect on buzz modes
Buzz is disabled during sleep, with bandgap powered down. No periodic wakeup of the
bandgap during sleep.
BUZZ bandgap during power down
Bandgap is always powered even during sleep.
1.95 ms (512 Hz)
15.6 ms (64 Hz)
125 ms (8 Hz)
1 s (1 Hz)
6 MHz IMO
750 kHz
1.5 MHz
3 MHz
6 MHz
375 kHz
187.5 kHz
46.9 kHz
23.4 kHz
No Buzz
RW : 0
5
12 MHz IMO
1.5 MHz
3 MHz
6 MHz
12 MHz
750 kHz
375 kHz
93.7 kHz
46.8 kHz
4
Sleep[1:0]
RW : 0
External Clock
EXTCLK / 8
EXTCLK / 4
EXTCLK / 2
EXTCLK / 1
EXTCLK / 16
EXTCLK / 32
EXTCLK / 128
EXTCLK / 256
3
Register Definitions on page 94
2
1,E0h
Reset State
CPU Speed[2:0]
RW : 001b
1
OSC_CR0
1,E0h
0
in the
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