CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 67

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

9.4.2
Once asleep, the only event that can wake the system up is
an interrupt. The Global Interrupt Enable of the CPU flag
register does not need to be set. Any unmasked interrupt
will wake the system up. It is optional for the CPU to actually
take the interrupt after the wakeup sequence.
The wake up sequence is synchronized to the 32 kHz clock
for purposes of sequencing a startup delay, to allow the
Flash memory module enough time to power up before the
CPU asserts the first read access. Another reason for the
delay is to allow the IMO, bandgap, and LVD/POR circuits
time to settle before actually being used in the system. As
shown in
1. The wake up interrupt occurs and is synchronized by the
PSoC CY8C20x34 TRM, Version 1.0
negative edge of the 32 kHz clock.
LVD/PPOR
BANDGAP
BANDGAP
BANDGAP
POR/LVD/
LVD/POR
CPUCLK/
6/12 Mhz
SAMPLE
SAMPLE
ENABLE
CLK32K
SLEEP
Figure
BRQ
CPU
BRA
INT
PD
Wake Up Sequence
9-2, the wake up sequence is as follows.
(Not to Scale)
Sleep timer or GPIO
interrupt occurs.
Figure 9-2. Wakeup Sequence
32K clock and PD is negated to
Interrupt is double sampled by
system.
LVD/PPOR is valid
2. At the following positive edge of the 32 kHz clock, the
3. At the next positive edge of the 32 kHz clock, the values
4. At the following negative edge of the 32 kHz clock (after
The wake up times (interrupt to CPU operational) ranges
from two to three 32 kHz cycles or 61 - 92 µs (nominal).
system-wide PD signal is negated. The Flash memory
module, IMO, and bandgap any POR/LVD circuits are all
powered up to a normal operating state.
of the bandgap are settled and sampled.
about 15 µs, nominal), the values of the POR/LVD sig-
nals have settled and are sampled. The BRQ signal is
negated by the sleep logic circuit. On the following CPU
clock, BRA is negated by the CPU and instruction exe-
cution resumes.
CPU is restarted after
75 µs (nominal).
Sleep and Watchdog
67