CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 51

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

5.3.4
The Interrupt Vector Clear Register (INT_VC) returns the
next pending interrupt and clears all pending interrupts
when written.
Bits 7 to 0: Pending Interrupt[7:0]. When the register is
read, the least significant byte (LSB) of the highest priority
pending interrupt is returned. For example, if the GPIO and
I2C interrupts were pending and the INT_VC register was
read, the value 14h is read. However, if no interrupts were
pending, the value 00h is returned. This is the reset vector in
the interrupt table; however, reading 00h from the INT_VC
register should not be considered an indication that a sys-
tem reset is pending. Rather, reading 00h from the INT_VC
register simply indicates that there are no pending inter-
rupts. The highest priority interrupt, indicated by the value
5.3.5
PSoC CY8C20x34 TRM, Version 1.0
0,E2h
LEGEND
C Clearable register or bits.
Address
“CPU_F Register” on page
INT_VC Register
Related Registers
INT_VC
Name
Bit 7
32.
Bit 6
Bit 5
Pending Interrupt[7:0]
Bit 4
returned by a read of the INT_VC register, is removed from
the list of pending interrupts when the M8C services an
interrupt.
Reading the INT_VC register has limited usefulness. If inter-
rupts are enabled, a read to the INT_VC register would not
be able to determine that an interrupt was pending before
the interrupt was actually taken. However, while in an inter-
rupt service routine, a user may wish to read the INT_VC
register to see what the next interrupt are. When the
INT_VC register is written, with any value, all pending and
posted interrupts are cleared by asserting the clear line for
each interrupt.
For additional information, refer to the
page
177.
Bit 3
Bit 2
Bit 1
INT_VC register on
Interrupt Controller
Bit 0
Access
RC : 00
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