CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 48

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Interrupt Controller
4. Program execution vectors to the interrupt table. Typi-
5. The ISR executes. Note that interrupts are disabled
6. The ISR ends with a RETI instruction. This pops the Flag
7. Execution resumes at the next instruction, after the one
Interrupt Latency. The time between the assertion of an
enabled interrupt and the start of its ISR is calculated using
this equation:
For example, if the 5-cycle JMP instruction is executing
when an interrupt becomes active, the total number of CPU
clock cycles before the ISR begins are:
In the example above, at 24 MHz, 25 clock cycles take
1.042 µs.
Interrupt Priority. Interrupt priorities only come into consid-
eration if more than one interrupt is pending during the same
instruction cycle. In this case, the priority encoder (see
Figure
pendingpriority interrupt.
5.1.1
An interrupt is posted when its interrupt conditions occur.
This results in the flip-flop in
interrupt remains posted until the interrupt is taken or until it
is cleared by writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enabled by set-
ting its interrupt mask bit (in the appropriate INT_MSKx reg-
ister). All pending interrupts are processed by the Priority
48
Time for M8C to change program counter to interrupt address +
cally, a LJMP instruction in the interrupt table sends exe-
cution to the user's interrupt service routine (ISR) for this
interrupt. (See
since GIE = 0. In the ISR, interrupts can be re-enabled if
desired by setting GIE = 1 (take care to avoid stack over-
flow in this case).
register, PCL, and PCH from the stack, restoring those
registers. The restored Flag register re-enables inter-
rupts since GIE = 1 again.
that occurred before the interrupt. However, if there are
more pending interrupts, the subsequent interrupts are
processed before the next normal program instruction.
5-1) generates an interrupt vector for the highest
Time for LJMP instruction in interrupt table to execute.
Time for current instruction to finish +
(7 cycles for LJMP) = 21 to 25 cycles.
Posted versus Pending Interrupts
(13 cycles for interrupt routine) +
(1 to 5 cycles for JMP to finish) +
“Instruction Set Summary” on page
Latency =
Figure 5-1
clocking in a ‘1’. The
Equation 1
Equation 2
28.)
Encoder to determine the highest priority interrupt which is
taken by the M8C if the Global Interrupt Enable bit is set in
the CPU_F register.
Disabling an interrupt by clearing its interrupt mask bit (in
the INT_MSKx register) does not clear a posted interrupt,
nor does it prevent an interrupt from being posted. It simply
prevents a posted interrupt from becoming pending.
It is especially important to understand the functionality of
clearing posted interrupts, if the configuration of the PSoC
device is changed by the application.
For example, if a block has a posted interrupt when it is
enabled, and then disabled, the posted interrupt remains. It
is good practice to use the INT_CLR register to clear posted
interrupts before enabling or re-enabling a block.
5.2
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in the PSoC devices. Interrupts for all the
digital blocks and each of the analog columns are available,
as well as interrupts for supply voltage, sleep, variable
clocks, and a general GPIO (pin) interrupt.
The registers associated with the interrupt controller allow
interrupts to be disabled either globally or individually. The
registers also provide a mechanism by which a user can
clear all pending and posted interrupts, or clear individual
posted or pending interrupts. A software mechanism is pro-
vided to set individual interrupts. Setting an interrupt by way
of software is very useful during code development, when
one may not have the complete hardware system necessary
to generate a real interrupt.
This table lists the interrupts and priorities that are available
in the PSoC devices.
Table 5-1. PSoC Device Interrupt Table
0 (Highest)
8 (Lowest)
Interrupt
Priority
1
2
3
4
5
6
7
Application Overview
Interrupt
Address
000Ch
001Ch
0000h
0004h
0008h
0010h
0014h
0018h
0020h
PSoC CY8C20x34 TRM, Version 1.0
Interrupt Name
Reset
Supply Voltage Monitor
Analog
CapSense
Timer
GPIO
SPI
I2C
Sleep Timer