CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 19

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

This chapter lists, describes, and illustrates all pins and pinout configurations for the CY8C20x34 PSoC device. For up-to-
date ordering, pinout, and packaging information, refer to the individual PSoC device’s data sheet or go to
http://www.cypress.com/psoc.
1.1
The CY 8C20x34 PSoC device is available in a variety of packages. Every port pin (labeled with a “P”), except for Vss, Vdd,
and XRES in the following tables and illustrations, is capable of Digital IO.
1.1.1
Table 1-1. 24-Pin Part Pinout (QFN**)
PSoC CY8C20x34 TRM, Version 1.0
LEGEND A = Analog, I = Input, O = Output, H = 5 mA High Output Drive.
Pin
No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1.
1
2
3
4
5
6
7
8
9
Digital
IOH
IOH
IOH
IOH
IOH
IOH
IOH
IOH
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
** The center pad on the QFN package should be connected to ground (Vss)
Power
Power
Type
Input
for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other sig-
nal.
Pinouts
Pin Information
24-Pin Part Pinout
Analog
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]
NC
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
P0[7]
P0[5]
P0[3]
P0[1]
Name
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK
CLK*, I2C SCL, SPI MOSI
No connection
Ground connection
DATA*, I2C SDA
Optional external clock input (EXTCLK)
Active high external reset with internal pull down
Analog bypass
Supply voltage
Integrating input
Description
AI, I2C SDA, SPI MISO, P1[5]
AI, I2C SCL, SPI SS, P1[7]
AI, SPI CLK, P1[3]
CY8C20334 24-Pin PSoC Device
AI, P2[5]
AI, P2[3]
AI, P2[1]
2
1
3
4
5
6
(Top View)
QFN
18
17
16
15
14
13
P0[4], AI
P0[2], AI
P0[0], AI
P2[0], AI
P1[6], AI
XRES
19