CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 74

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

CapSense Module
capacitance measurement sensitivity. The CS_SLEW regis-
ter controls this mode.
Figure 10-3. Second Phase of Proximity Detection (Cap
Connected to Global)
74
Comparator
Vr
M8C Read
IDAC
Reference
Buffer
Mux
Mux
Iout
LP Filter
Vr
Conn. to
Closed
ground
CSCLK
Cinternal
Cs1
Cs2
Csn
10.1.2
The internal current DAC provides a bias current for use
with the relaxation oscillator (RO), or for capacitance mea-
surement in the proximity detect mode. It can also be set to
supply a sinking or sourcing current to any IO pin through
the analog global bus connection.
The IDAC current is set by the 8-bit IDAC_D register. In
addition, the two IRANGE bits in the CS_CR2 register pro-
vide additional prescaling range.
10.1.3
The CapSense Counter block (see
to implement the relaxation oscillator algorithm. The hard-
ware consists of two 8-bit up-counters with capture that can
be optionally chained into a single 16-bit capture counter
and an additional 6-bit timer.
In the relaxation algorithm, a 6-bit timer is clocked by the
relaxation oscillator. A 16-bit chained counter is formed and
clocked by CSCLK, a divided version of the internal main
oscillator (IMO). In this configuration, the counters are
enabled simultaneously with a write to the enable bit. On ter-
minal count of the 6-bit RO counter, the contents of the 16-
bit counter are captured. Changes in this count then indicate
capacitance changes.
The CapSense Counter block is optimized to implement the
relaxation oscillator algorithm. The hardware consists of two
8-bit counters capable of being chained into a 16-bit counter.
For a clear understanding of this architecture see the block
diagram in figure 10-7.
IMO/2
IMO/4
IMO/8
IMO
EN
CLKSEL[1:0]
Figure 10-4. CapSense Counter Block Diagram
0
1
2
3
Low Byte Counter
CSCLK
Counter
IDAC
CapSense Counter
8-Bit
Up
CO
COL
RLO
PSoC CY8C20x34 TRM, Version 1.0
CHAIN
RLOSEL
0
1
Figure
High Byte Counter
EN
CS_INT
COHR
COLR
10-4) is optimized
Counter
IN
CSOUT[1:0]
8-Bit
Up
CO
0
1
2
3
COH
To Pin