CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 102

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

I2C Slave
Table 14-4. I2C_SCR Status and Control Register
Bit 5: Stop Status. Stop status is set on detection of an I2C
Stop condition. This bit is sticky, which means that it will
remain set until a ‘0’ is written back to it by the firmware.
This bit may only be cleared if the Byte Complete status bit
is set. If the Stop Interrupt Enable bit is set, an interrupt is
also generated on Stop detection. It is never automatically
cleared.
Using this bit, a slave can distinguish between a previous
Stop or Restart on a given address byte interrupt.
Bit 4: ACK. This control bit defines the acknowledge data
bit that is transmitted out in response to a received byte.
When receiving, a Byte Complete interrupt is generated
after the eighth data bit is received. On the subsequent write
to this register to continue (or terminate) the transfer, the
state of this bit will determine the next bit of data that is
transmitted. It is active high . A ‘1’ will send an ACK and a
‘0’ will send a NACK. A Slave receiver sends a NACK to
inform the master that it cannot receive any more bytes.
102
Bit
7
5
4
3
2
1
0
Access
RC
RC
RW
RC
RW
RC
RC
Description
Bus Error
1 = A misplaced Start or Stop condition was detected.
This status bit must be cleared by firmware with a write of
‘0’ to the bit position. It is never cleared by the hardware.
Stop Status
1 = A Stop condition was detected.
This status bit must be cleared by firmware with a write of
‘0’ to the bit position. It is never cleared by the hardware.
ACK: Acknowledge Out
0 = NACK the last received byte.
1 = ACK the last received byte.
This bit is automatically cleared by hardware on the fol-
lowing Byte Complete event.
Address
1 = The transmitted or received byte is an address.
This status bit must be cleared by firmware with a write of
‘0’ to the bit position.
Transmit
0 = Receive Mode.
1 = Transmit Mode.
This bit is set by firmware to define the direction of the
byte transfer.
Any Start detect will automatically clear this bit.
LRB: Last Received Bit
The value of the ninth bit in a Transmit sequence, which is
the acknowledge bit from the receiver.
1 = Last transmitted byte was NACK’ed by the receiver.
Any Start detect will automatically clear this bit.
Byte Complete
Transmit Mode:
1 = 8 bits of data have been transmitted and an ACK or
NACK has been received.
Receive Mode:
1 = 8 bits of data have been received.
Any Start detect will automatically clear this bit.
0 = Last transmitted byte was ACK’ed by the receiver.
Bit 3: Address. This bit is set when an address has been
received. This consists of a Start or Restart, and an address
byte.
In Slave mode, when this status is set, firmware will read the
received address from the data register and compare it with
its own address. If the address does not match, the firmware
will write a NACK indication to this register. No further inter-
rupts will occur until the next address is received. If the
address does match, firmware must ACK the received byte,
then Byte Complete interrupts are generated on subsequent
bytes of the transfer.
Bit 2: Transmit. This bit sets the direction of the shifter for
a subsequent byte transfer. The shifter is always shifting in
data from the I2C bus, but a write of ‘1’ enables the output of
the shifter to drive the SDA output line. Since a write to this
register initiates the next transfer, data must be written to the
data register prior to writing this bit. In Receive mode, the
previously received data must have been read from the data
register before this write. Firmware derives this direction
from the RW bit in the received slave address.
This direction control is only valid for data transfers. The
direction of address bytes is determined by the hardware.
Bit 1: LRB. Last Received Bit. This is the last received bit
in response to a previously transmitted byte. In Transmit
mode, the hardware will send a byte from the data register
and clock in an acknowledge bit from the receiver. On the
subsequent byte complete interrupt, firmware will check the
value of this bit. A ‘0’ is the ACK value and a ‘1’ is a NACK
value. The meaning of the LRB depends on the current
operating mode.
Bit 0: Byte Complete. The I2C hardware operates on a
byte basis. In Transmit mode, this bit is set and an interrupt
is generated at the end of nine bits (the transmitted byte +
the received ACK). In Receive mode, the bit is set after the
eight bits of data are received. When this bit is set, an inter-
rupt is generated at these data sampling points, which are
associated with the SCL input clock rising (see details in
“Timing Diagrams” on page
responds with a write back to this register before the subse-
quent falling edge of SCL (which is approximately one-half
bit time), the transfer will continue without interruption. How-
ever, if the PSoC device is unable to respond within that
time, the hardware will hold the SCL line low, stalling the I2C
bus. A subsequent write to the I2C_SCR register will
release the stall.
For additional information, refer to the
page
‘0’: ACK. The master wants to read another byte. The
slave should load the next byte into the I2C_DR register
and set the transmit bit in the I2C_SCR register to con-
tinue the transfer.
‘1’: NACK. The master is done reading bytes. The slave
will revert to IDLE state on the subsequent I2C_SCR
write (regardless of the value written).
171.
PSoC CY8C20x34 TRM, Version 1.0
103). If the PSoC device
I2C_SCR register on