CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 120

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

SPI
18.2.2.1
There are two 8-bit Data registers and one 8-bit Control/Status register.
Receive registers in the context of SPIM operation.
Table 18-2. SPIM Data Register Descriptions
18.2.2.2
There are two 8-bit Data registers and one 8-bit Control/Status register.
Receive registers in the context of SPIS operation.
Table 18-3. SPIS Data Register Descriptions
120
SPI_TXR
SPI_RXR
SPI_TXR
SPI_RXR
Name
Name
TX Buffer
RX Buffer
TX Buffer
RX Buffer
SPI Master Data Register Definitions
SPI Slave Data Register Definitions
Function
Function
Write only register.
If no transmission is in progress and this register is written to, the data from this register is loaded into the Shift register, on
the following clock edge, and a transmission is initiated.
buffer for TX data.
This register should only be written to when TX Reg Empty status is set and the write clears the TX Reg Empty status bit in
the Control register. When the data is transferred from this register to the Shift register, then TX Reg Empty status is set.
Read only register.
When a byte transmission/reception is complete, the data in the shifter is transferred into the RX Buffer register and RX Reg
Full status is set in the Control register.
A read from this register clears the RX Reg Full status bit in the Control register.
Write only register.
This register should only be written to when TX Reg Empty status is set and the write clears the TX Reg Empty status bit in
the Control register. When the data is transferred from this register to the Shift register, then TX Reg Empty status is set.
Read only register.
When a byte transmission/reception is complete, the data in the shifter is transferred into the RX Buffer register and RX Reg
Full status is set in the Control register.
A read from this register clears the RX Reg Full status bit in the Control register.
Description
Description
Table 18-2
Table 18-3
If a transmission is currently in progress, this register serves as a
explains the meaning of the Transmit and
explains the meaning of the Transmit and
PSoC CY8C20x34 TRM, Version 1.0