CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 159

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

20.3.19 CS_STAT
This register controls the CapSense counter options.
The interrupt mask bits should never be modified while the block is enabled. If modification to bits 3 to 0 is necessary while
the block is enabled, then special attention must be paid to ensure that the status bits, bits 7 to 4, are not accidentally cleared.
This can be done by writing a ‘1’ to all of the status bits when writing to the mask bits.
For additional information, refer to the
Bit
7
6
5
4
3
2
1
0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
CS_STAT : 0,A6h
Access : POR
Bit Name
INS
COLS
COHS
PPS
INM
COLM
COHM
PPM
Name
CapSense Status Register
RC : 0
INS
7
RC : 0
COLS
6
Description
Input Status
0
1
Counter Carry Out Low Status
0
1
Counter Carry Out High Status
0
1
Pulse Width/Period Measurement Status
0
1
Input Interrupt/Mask
0
1
Counter Carry Out Low Interrupt Mask
0
1
Counter Carry Out High Interrupt Mask
0
1
Pulse Width/Period Measurement Interrupt Mask
0
1
Register Definitions on page 76
No event detected
A rising edge on the selected input was detected. Cleared by writing a ‘0’ to this bit.
No event detected
A carry out from the low byte counter was detected. Cleared by writing a ‘0’ back to this bit.
No event detected
A carry out from the high byte counter was detected. Cleared by writing a ‘0’ back to this bit.
No event detected
A pulse width or period measurement was completed. Cleared by writing a ‘0’ back to this
bit.
Disabled
Input event is enabled to assert the block interrupt.
Disabled
Counter carry out low is enabled to assert the block interrupt.
Disabled
Counter carry out high is enabled to assert the block interrupt.
Disabled
Completion of a pulse width or period measurement is enabled to assert the block interrupt.
RC : 0
COHS
5
RC : 0
PPS
4
in the CapSense Module chapter .
RW : 0
INM
3
RW : 0
COLM
2
RW : 0
COHM
1
0,A6h
RW : 0
CS_STAT
0,A6h
PPM
0
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