CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 40

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Supervisory ROM (SROM)
The following code example puts the correct value in KEY1
and KEY2. The code is preceded by a HALT, to force the
program to jump directly into the setup code and not acci-
dentally run into it.
1.
2. SSCOP: mov [KEY1], 3ah
3.
4.
5.
6.
4.1.1
The SROM has the following additional feature.
Return Codes: These aid in the determination of success
or failure of a particular function. The return code is stored in
KEY1’s position in the parameter block. The CheckSum and
TableRead functions do not have return codes because
KEY1’s position in the parameter block is used to return
other data.
Table 4-3. SROM Return Code Meanings
Note Read, write, and erase operations may fail if the target
block is read or write protected. Block protection levels are
set during device programming and cannot be modified from
code in the PSoC device.
4.1.2
4.1.2.1
The SROM function SWBootReset is responsible for transi-
tioning the device from a reset state to running user code.
See
what events causes the SWBootReset function to execute.
The SWBootReset function is executed whenever the
SROM is entered with an M8C accumulator value of 00h;
the SRAM parameter block is not used as an input to the
function. This happens, by design, after a hardware reset
because the M8C's accumulator is reset to 00h or when
user code executes the SSC instruction with an accumulator
value of 00h.
If the checksum of the calibration data is valid, the
SWBootReset function ends by setting the internal M8C reg-
isters to 00h, writing 00h to most SRAM addresses in SRAM
Page 0, and then begins to execute user code at address
0000h. (See
more information on which SRAM addresses are modified.)
40
Return Code Value
“System Resets” on page 109
00h
01h
02h
03h
Additional SROM Feature
SROM Function Descriptions
halt
mov X, SP
mov A, X
add A, 3
mov [KEY2], A
Table 4-4
SWBootReset Function
Success
Function not allowed due to level of protection on
the block.
Software reset without hardware reset.
Fatal error, SROM halted.
and the following paragraphs for
Description
for more information on
If the checksum is not valid, an internal reset is executed
and the boot process starts over. If this condition occurs, the
internal reset status bit (IRESS) is set in the CPU_SCR1
register.
In PSoC devices with more than 256 bytes of SRAM, no
SRAM is modified by the SWBootReset function in SRAM
pages numbered higher than ‘0’.
Table 4-4
Page 0 after a successful SWBootReset. A value of “xx”
indicates that the SRAM address is not modified by the
SWBootReset function. A hex value indicates that the
address should always have the indicated value after a suc-
cessful SWBootReset. A “??” indicates that the value, after
a SWBootReset, is determined by the value of the IRAMDIS
bit in the CPU_SCR1 register. If IRAMDIS is not set, these
addresses will be initialized to 00h. If IRAMDIS is set, these
addresses will not be modified by a SWBootReset after a
watchdog reset.
The IRAMDIS bit allows the preservation of variables even if
a watchdog reset (WDR) occurs. The IRAMDIS bit is reset
by all system resets except watchdog reset. Therefore, this
bit is only useful for watchdog resets and not general resets.
documents the value of all the SRAM addresses in
PSoC CY8C20x34 TRM, Version 1.0