CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 181

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

20.3.40 CPU_SCR1
This register is used to convey the status and control of events related to internal resets and watchdog reset.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved
bits should always be written with a value of ‘0’. For additional information, refer to the
System Resets chapter.
Bit
7
4
0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
CPU_SCR1: x,FEh
Access : POR
Bit Name
IRESS
SLIMO
IRAMDIS
Name
System Status and Control Register 1
IRESS
R : 0
7
6
Description
This bit is read only.
0
1
Reduces frequency of the internal main oscillator (IMO). This bit is reserved on PSoC devices that do
not support the slow IMO (see the
0
1
0
1
Boot phase only executed once.
Boot phase occurred multiple times.
IMO produces 12 MHz
Slow IMO (6 MHz)
SRAM is initialized to 00h after POR, XRES, and WDR.
Addresses 03h - D7h of SRAM Page 0 are not modified by WDR.
5
RW : 0
SLIMO
4
Architectural Description on page
3
Register Definitions on page 110
2
x,FEh
59).
1
CPU_SCR1
IRAMDIS
RW : 0
x,FEh
0
in the
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