CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 61

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

This chapter briefly explains the Internal Low Speed Oscillator (ILO) and its associated register. The Internal Low Speed
Oscillator produces a 32 kHz clock. For a quick reference of all PSoC registers in address order, refer to the
Reference chapter on page
8.1
The Internal Low Speed Oscillator (ILO) is an oscillator with a nominal frequency of 32 kHz. It is used to generate sleep wake-
up interrupts and watchdog resets. This oscillator can also be used as a clocking source for the digital PSoC blocks.
The oscillator operates in three modes: normal power, low power, and off. The Normal Power mode consumes more current
to produce a more accurate frequency. The Low Power mode is always used when the part is in a power down (sleep) state.
Low Power mode can be selected when the device is not asleep, but the oscillator’s output frequency is less accurate. The
Off mode turns the oscillator off.
8.2
The following register is associated with the Internal Low Speed Oscillator (ILO). The register description has an associated
register table showing the bit structure. The bits in the table that are grayed out are reserved bits and are not detailed in the
register description that follows. Reserved bits should always be written with a value of ‘0’.
8.2.1
The Internal Low Speed Oscillator Trim Register (ILO_TR)
sets the adjustment for the internal low speed oscillator.
The device-specific value, placed in the trim bits of this reg-
ister at boot time, is based on factory testing. It is strongly
recommended that the user not alter the values in the
register.
Bits 5 and 4: Bias Trim[1:0]. These bits are used to set
the bias current in the PTAT Current Source. Bit 5 gets
inverted, so that a medium bias is selected when both bits
are ‘0’. The bias current is set according to
PSoC CY8C20x34 TRM, Version 1.0
8.
Address
1,E9h
Architectural Description
Register Definitions
Internal Low Speed Oscillator (ILO)
ILO_TR Register
ILO_TR
Name
Bit 7
139.
Bit 6
Table
Bit 5
8-1.
Bias Trim[1:0]
Bit 4
Table 8-1. Bias Current in PTAT
Bits 3 to 0: Freq Trim[3:0]. These bits are used to trim the
frequency. Bit 0 is the LSb and bit 3 is the MSb. Bit 3 gets
inverted inside the register.
For additional information, refer to the
page
Medium Bias
Maximum Bias
Minimum Bias
Reserved
194.
Bit 3
Bias Current
Bit 2
Freq Trim[3:0]
Bit 1
Bias Trim [1:0]
ILO_TR register on
Bit 0
00b
01b
10b
11b
Access
W : 00
Register
61