CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 93

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

glitch-free transition and provides a full cycle of setup time
from SYSCLK to output disable. Once the current clock
selection is disabled, the enable of the newly selected clock
is double synchronized to that clock. After synchronization,
on the subsequent negative edge, SYSCLK is enabled to
output the newly selected clock.
PSoC CY8C20x34 TRM, Version 1.0
Figure 13-3. Switch from IMO to External Clock with the CPU Running with a CPU Clock Divider of One
External Clock
Extenal Clock
EXTCLK bit
Figure 13-2. Switch from IMO to the External Clock with a CPU Clock Divider of Two or Greater
CPUCLK
SYSCLK
EXTCLK
CPUCLK
SYSCLK
IOW_
IOW
IMO
IMO
disabled.
disabled.
IMO is
IMO is
External clock is
External clock is
In the 12 MHz case, as shown in
of IOW_ and thus the setting of the EXTCLKEN bit occurs
on the falling edge of SYSCLK. Since SYSCLK is already
low, the output is immediately disabled. Therefore, the setup
time from SYSCLK to disable is one-half SYSCLK.
enabled.
enabled.
Figure
13-3, the assertion
Digital Clocks
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