CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 37

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

3.2.3
The Stack Page Pointer Register (STK_PP) is used to set
the effective SRAM page for stack memory accesses in a
multi-SRAM page PSoC device.
Bit 0: Page Bit. This bit has the potential to affect two
types of memory access.
The purpose of this register is to determine which SRAM
page the stack is stored on. In the reset state, this register's
value is 0x00 and the stack will therefore be in SRAM Page
0. However, if the STK_PP register value is changed, the
next stack operation will occur on the SRAM page indicated
by the new STK_PP value. Therefore, the value of this reg-
ister should be set early in the program and never be
changed. If the program changes the STK_PP value after
3.2.4
The Index Page Pointer Register (IDX_PP) is used to set
the effective SRAM page for indexed memory accesses in a
multi-SRAM page PSoC device.
Bits 0: Page Bit. This bit allows instructions, which use the
source indexed and destination indexed address modes, to
operate on an SRAM page that is not equal to the current
SRAM page. However, the effect this register has on
3.2.5
The MVI Read Page Pointer Register (MVR_PP) is used to
set the effective SRAM page for MVI read memory accesses
in a multi-SRAM page PSoC device.
Bit 0: Page Bit. This bit is only used by the MVI A, [expr]
instruction, not to be confused with the MVI [expr], A instruc-
tion covered by the MVW_PP register. This instruction is
considered a read because data is transferred from SRAM
to the microprocessor's A register (CPU_A).
When an MVI A, [expr] instruction is executed in a device
with more than one page of SRAM, the SRAM address that
PSoC CY8C20x34 TRM, Version 1.0
0,D1h
0,D3h
0,D4h
Address
Address
Address
STK_PP
IDX_PP
MVR_PP
STK_PP Register
IDX_PP Register
MVR_PP Register
Name
Name
Name
Bit 7
Bit 7
Bit 7
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 4
Bit 4
Bit 4
the stack has grown, the program must ensure that the
STK_PP value is restored when needed.
Note The impact that the STK_PP register has on the stack
is independent of the SRAM Paging bits in the CPU_F regis-
ter.
The second type of memory accesses that the STK_PP reg-
ister affects are indexed memory accesses when the
CPU_F[7:6] bits are set to 11b. In this mode, source indexed
and destination indexed memory accesses are directed to
the stack SRAM page, rather than the SRAM page indicated
by the IDX_PP register or SRAM Page 0.
For additional information, refer to the
page
indexed addressing modes is only enabled when the
CPU_F[7:6] is set to 10b.
When CPU_F[7:6] is set to 10b and an indexed memory
access is made, the access is directed to the SRAM page
indicated by the value of the IDX_PP register.
See the STK_PP register description for more information
on other indexed memory access modes. For additional
information, refer to the
is read by the instruction is determined by the value of the
least significant bits in this register. However, the pointer for
the MVI A, [expr] instruction is always located in the current
SRAM page. See the PSoC Designer Assembly Language
User Guide for more information on the MVI A, [expr]
instruction.
The function of this register and the MVI instructions are
independent of the SRAM Paging bits in the CPU_F register.
For additional information, refer to the
page
166.
168.
Bit 3
Bit 3
Bit 3
Bit 2
Bit 2
Bit 2
IDX_PP register on page
Bit 1
Bit 1
Bit 1
Page Bit
Page Bit
MVR_PP register on
Page Bit
STK_PP register on
Bit 0
Bit 0
Bit 0
RAM Paging
167.
RW : 00
RW : 00
RW : 00
Access
Access
Access
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