CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 191

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

20.4.9
This register is used to set the trip points for the POR and LVD.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved
bits should always be written with a value of ‘0’. For additional information, refer to the
POR and LVD chapter.
Bit
5:4
3
2:0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
VLT_CR: 1,E3h
Access : POR
Bit Name
PORLEV[1:0]
LVDTBEN
VM[2:0]
Name
VLT_CR
Voltage Monitor Control Register
7
6
Description
Sets the POR level per the DC electrical specifications in the PSoC device data sheet.
00b
01b
10b
11b
Enables reset of CPU speed register by LVD comparator output.
0
1
Sets the LVD levels per the DC electrical specifications in the PSoC device data sheet, for those
PSoC devices with this feature.
000b
001b
010b
011b
100b
101b
110b
111b
POR level for 2.4 V operation (refer to the PSoC device data sheet)
POR level for 2.7V operation (refer to the PSoC device data sheet)
POR level for 3.0V operation
Reserved
Disables CPU speed throttle-back.
Enables CPU speed throttle-back.
Lowest voltage setting
.
.
.
Highest voltage setting
5
PORLEV[1:0]
RW : 0
4
LVDTBEN
RW : 0
3
Register Definitions on page 115
2
1,E3h
VM[2:0]
RW : 0
1
1,E3h
VLT_CR
0
in the
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