CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 114

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

System Resets
16.4.4
Timing and functionality details are summarized in
PPOR, and XRES, while
Table 16-1. Details of Functionality for Various Resets
a. CPU reset is released after synchronization with the CPU clock.
b. Measured from CPU reset release to execution of the code at Flash address 0x0000.
16.5
The ILO block drives the CLK32K clock used to time most
events during the reset sequence. This clock is powered
down by IPOR but not by any other reset. The sleep timer
provides interval timing.
While POR or XRES assert, the IMO is powered off to
reduce start-up power consumption.
During and following IRES (for 64 ms nominally), the IMO is
powered off for low average power during slow supply
ramps.
During and after POR or XRES, the bandgap circuit is pow-
ered up.
Following IRES, the bandgap circuit is only powered up
occasionally to refresh the sampled bandgap voltage value.
This sampling follows the same process used during sleep
mode.
The IMO is always on for at least one CLK32K cycle before
CPU reset is de-asserted.
114
Reset Length
Low Power (IMO Off) During Reset?
Low Power Wait Following Reset?
CLK32K Cycles from End of Reset to
CPU Reset De-asserts
Register Reset
(See next line for CPU_SCR0,
CPU_SCR1)
Reset Status Bits in CPU_SCR0,
CPU_SCR1
Bandgap Power
Boot Time
b
Power Modes
Reset Details
Item
a
Figure 16-3
shows signaling for WDR and IRES.
IPOR (Part of POR)
Clear IRAMDIS
While POR=1
Clear WDRS,
Set PORS,
2.2 ms
Yes
512
No
On
All
Table
All, except PPOR does not
16-1.
PPOR (Part of POR)
30-60 µ s (1-2 clocks)
While PPOR=1, plus
reset Bandgap Trim
Clear IRAMDIS
Clear WDRS,
Set PORS,
Figure 16-4
register
2.2 ms
Yes
On
No
1
shows some of the relevant signals for IPOR,
Clear IRAMDIS
While XRES=1
Clear WDRS,
Set PORS,
PSoC CY8C20x34 TRM, Version 1.0
2.2 ms
XRES
Yes
No
On
All
8
IRAMDIS unchanged
30 µ s (1 clock)
Clear PORS,
Set WDRS,
2.2 ms
WDR
No
No
On
All
1