CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 100

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

I2C Slave
14.3
The following registers are associated with I2C Slave and are listed in address order. Each register description has an asso-
ciated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and
are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’. For a com-
plete table of I2C registers, refer to the
14.3.1
The I2C Configuration Register (I2C_CFG) is used to set
the basic operating modes, baud rate, and selection of inter-
rupts.
The bits in this register control baud rate selection and
optional interrupts. The values are typically set once for a
given configuration. The bits in this register are all RW.
Table 14-1. I2C_CFG Configuration Register
Bit 6: PSelect. Pin Select. With the default value of zero,
the I2C pins are P1[7] for clock and P1[5] for data. When
this bit is set, the pins for I2C switch to P1[1] for clock and
P1[0] for data. This bit may not be changed while the Enable
bit is set. However, the PSelect bit may be set at the same
time as the enable bits. The two sets of pins that may be
used on I2C are not equivalent. The default set, P1[7] and
P1[5], are the preferred set. The alternate set, P1[1] and
P1[0], are provided so that I2C may be used with 8-pin
PSoC devices.
If In-circuit System Serial Programming (ISSP
the alternate I2C pin set is also used, it is necessary to take
into account the interaction between the PSoC Test Control-
ler and the I2C bus. The interface requirements for ISSP
should be reviewed to ensure that they are not violated.
Even if ISSP is not used, pins P1[1] and P1[0] will respond
differently to a POR or XRES event than other IO pins. After
an XRES event, both pins are pulled down to ground by
going into the resistive zero drive mode, before reaching the
100
0,D6h
6
4
3:2
Bit
Address
RW
RW
RW
Access
Register Definitions
I2C_CFG
I2C_CFG Register
I2C Pin Select
0 = P1[7], P1[5]
1 = P1[1], P1[0]
Stop IE
Stop interrupt enable.
0 = Disabled.
1 = Enabled. An interrupt is generated on the
detection of a Stop Condition.
Clock Rate
00 = 100K Standard Mode
01 = 400K Fast Mode
10 = 50K Standard Mode
11 = Reserved
Name
Bit 7
Description
PSelect
Bit 6
“Summary Table of the System Resource Registers” on page
®
) is used and
Bit 5
Slave
Slave
Slave
Mode
Stop IE
Bit 4
High-Z Drive mode. After a POR event, P1[0] will drive out a
one, then go to the resistive zero state for some time, and
finally reach the High-Z drive mode state. After POR, P1[1]
will go into a resistive zero state for a while, before going to
the High-Z Drive mode.
Bit 4: Stop IE. Stop Interrupt Enable. When this bit is set, a
slave can interrupt on Stop detection. The status bit associ-
ated with this interrupt is the Stop Status bit in the I2C_SCR
register. When the Stop Status bit transitions from ‘0’ to ‘1’,
the interrupt is generated. It is important to note that the
Stop Status bit is not automatically cleared. Therefore, if it is
already set, no new interrupts are generated until it is
cleared by firmware.
Bits 3 and 2: Clock Rate[1:0]. These bits offer a selection
of three sampling and bit rates. All block clocking is based
on the SYSCLK input, which is nominally 12 MHz or 6 MHz
(unless the PSoC device is in external clocking mode). The
sampling rate and the baud rate are determined as follows:
The nominal values, when using the internal 12 MHz or 6
MHz oscillator, are shown in
Table 14-2. I
When clocking the input with a frequency other than 6/12
MHz (for example, clocking the PSOC device with an exter-
nal clock), the baud rates and sampling rates will scale
00b
01b
10b
11b
Sample Rate = SYSCLK/Pre-scale Factor
Baud Rate = 1/(Sample Rate x Samples per Bit)
0
1
0
1
0
1
0
1
Bit 3
Clock Rate[1:0]
Standard
Fast
Standard
Reserved
2
C Clock Rates
Bit 2
/8
/4
/2
/1
/8
/4
PSoC CY8C20x34 TRM, Version 1.0
16
16
32
Table
Bit 1
1.5 MHz/
667 ns
6 MHz/
167 ns
1.5 MHz/
667 ns
14-2.
90.
Enable
Bit 0
93.75 kHz
375 kHz
46.8 kHz
Access
RW : 00
5.3 µ s
1.33 µ s
10.7 µ s