CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 110

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

System Resets
16.2.2
During External Reset (XRES=1), both P1[0] and P1[1] drive
resistive low (0). After XRES de-asserts, these pins continue
to drive resistive low for another 8 sleep clock cycles
(approximately 200 µ s). After this time, both pins transition
to a high impedance state and normal CPU operation
begins. This is illustrated in
16.3
The following registers are associated with the PSoC System Resets and are listed in address order. Each register descrip-
tion has an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are
reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value
of ‘0’. For a complete table of system reset registers, refer to the
page
16.3.1
The System Status and Control Register 1 (CPU_SCR1) is
used to convey the status and control of events related to
internal resets and watchdog reset.
Bit 7: IRESS. Internal Reset Status. This bit is a read only
bit that may be used to determine if the booting process
occurred more than once.
When this bit is set, it indicates that the SROM SWBootRe-
set code was executed more than once. If this bit is not set,
the SWBootReset was executed only once. In either case,
the SWBootReset code will not allow execution from code
stored in Flash until the M8C core is in a safe operating
mode with respect to supply voltage and Flash operation.
There is no need for concern when this bit is set. It is pro-
vided for systems which may be sensitive to boot time, so
that they can determine if the normal one-pass boot time
was exceeded. For more information on the SWBootReest
code see the
page
110
x,FEh
LEGEND
x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used.
# Access is bit specific. Refer to the
Address
90.
39.
Register Definitions
CPU_SCR1
GPIO Behavior on External Reset
CPU_SCR1 Register
Name
Supervisory ROM (SROM) chapter on
IRESS
Bit 7
Figure
Register Reference chapter on page 139
16-2.
Bit 6
Bit 5
SLIMO
Bit 4
for additional information.
Figure 16-2. P1[1:0] Behavior on External Reset (XRES)
Bit 4: SLIMO. Slow IMO. When set, this bit allows the
active power dissipation of the PSoC device to be reduced
by slowing down the IMO from 12 MHz to 6 MHz. The IMO
trim value must also be changed when SLIMO is set (see
“Engaging Slow IMO” on page
clocking mode, the IMO is the source for SYSCLK; there-
fore, when the speed of the IMO changes so will SYSCLK.
Bit 0: IRAMDIS. Initialize RAM Disable. This bit is a control
bit that is readable and writeable. The default value for this
bit is ‘0’, which indicates that the maximum amount of SRAM
should be initialized on watchdog reset to a value of 00h.
When the bit is ‘1’, the minimum amount of SRAM is initial-
ized after a watchdog reset. For more information on this bit,
see the
For additional information, refer to the
on page
XRES
P1[0]
P1[1]
“Summary Table of the System Resource Registers” on
Bit 3
“SROM Function Descriptions” on page
181.
Bit 2
PSoC CY8C20x34 TRM, Version 1.0
R0
R0
T1 = 8 Sleep Clock Cycles
T1
(approximately 200 µs)
Bit 1
59). When not in external
IRAMDIS
CPU_SCR1 register
Bit 0
HiZ
HiZ
40.
Access
# : 00