CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 50

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Interrupt Controller
5.3.2
The Interrupt Mask Register (INT_MSK0) is used to enable
the individual interrupt sources’ ability to create pending
interrupts.
If cleared, each bit in an INT_MSK0 register prevents a
posted interrupt from becoming a pending interrupt (input to
the priority encoder). However, an interrupt can still post
even if its mask bit is zero. All INT_MSK0 bits are indepen-
dent of all other INT_MSK0 bits.
If an INT_MSK0 bit is set, the interrupt source associated
with that mask bit may generate an interrupt that will
become a pending interrupt. For example, if INT_MSK0[4] is
set and at least one GPIO pin is configured to generate an
interrupt, the interrupt controller will allow a GPIO interrupt
request to post and become a pending interrupt for the M8C
to respond to. If a higher priority interrupt is generated
before the M8C responds to the GPIO interrupt, the higher
priority interrupt is responded to before the GPIO interrupt.
Each interrupt source may require configuration at a block
level. Refer to the corresponding chapter for each interrupt
for any additional configuration information.
Bit 7: I2C. This bit allows I2C interrupts to be enabled or
masked.
5.3.3
The Interrupt Software Enable Register (INT_SW_EN) is
used to enable software interrupts.
50
0,E0h
0,E1h
Address
Address
INT_MSK0
INT_SW_EN
INT_MSK0 Register
INT_SW_EN Register
Name
Name
Bit 7
Bit 7
I2C
Sleep
Bit 6
Bit 6
Bit 5
Bit 5
SPI
GPIO
Bit 4
Bit 4
Bit 6: Sleep. This bit allows sleep interrupts to be enabled
or masked.
Bit 5: SPI. This bit allows SPI interrupts to be enabled or
masked.
Bit 4: GPIO. This bit allows GPIO interrupts to be enabled
or masked.
Bit 3: Timer. This bit allows Timer interrupts to be enabled
or masked.
Bit 2: CapSense. This bit allows CapSense interrupts to be
enabled or masked.
Bit 1: Analog. This bit allows analog interrupts to be
enabled or masked.
Bit 0: V Monitor. This bit allows voltage monitor interrupts
to be enabled or masked.
For additional information, refer to the
on page
Bit 0: ENSWINT. This bit is a special non-mask bit that
controls the behavior of the INT_CLR0 register. See the
INT_CLR0 register in this section for more information.
For additional information, refer to the
on page
175.
176.
Timer
Bit 3
Bit 3
CapSense
Bit 2
Bit 2
PSoC CY8C20x34 TRM, Version 1.0
Analog
Bit 1
Bit 1
INT_SW_EN register
INT_MSK0 register
ENSWINT
V Monitor
Bit 0
Bit 0
RW : 00
RW : 00
Access
Access