CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 58

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

General Purpose IO (GPIO)
6.2.3
The Port Drive Mode Bit Registers (PRTxDM0 and
PRTxDM1) are used to specify the Drive mode for GPIO
pins.
Bits 7 to 0: Drive Mode x[7:0]. In the PRTxDMx registers
there are four possible drive modes for each port pin. Two
mode bits are required to select one of these modes, and
these two bits are spread into two different registers
(PRTxDM0 and PRTxDM1). The bit position of the effected
port pin (for example, Pin[2] in Port 0) is the same as the bit
position of each of the two drive mode register bits that con-
trol the Drive mode for that pin (for example, bit[2] in
PRT0DM0 and bit[2] in PRT0DM1). The two bits from the
two registers are treated as a group. These are referred to
as DM1 and DM0, or together as DM[1:0]. Drive modes are
shown in
For analog IO, the Drive mode should be set to the High-Z
analog mode, 10b. The 10b mode disables the block’s digi-
tal input buffer so no crowbar current flows, even when the
analog input is not close to either power rail. If the 10b Drive
mode is used, the pin will always be read as a zero by the
CPU and the pin will not be able to generate a useful inter-
6.2.4
The Input/Output Configuration Register (IO_CFG) is used
to configure the Port 1 output regulator and set the Interrupt
mode for all GPIO.
Bit 1: REG_EN. The Register Enable bit (REG_EN) con-
trols the regulator on Port 1 outputs.
58
1,xxh
1,xxh
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
1,DCh
Address
Address
refer to the
Table
PRTxDM0
PRTxDM1
IO_CFG
“Core Register Summary” on page
PRTxDMx Registers
IO_CFG Register
Name
Name
6-2.
Bit 7
Bit 7
Bit 6
Bit 6
24.
Bit 5
Bit 5
Bit 4
Bit 4
Drive Mode 0[7:0]
Drive Mode 1[7:0]
rupt. (It is not strictly required that a High-Z mode be
selected for analog operation.)
When digital inputs are needed on the same pin as analog
inputs, the 11b Drive mode should be used with the corre-
sponding data bit (in the PRTxDR register) set high.
Table 6-2. Pin Drive Modes
The GPIO provides a default Drive mode of high imped-
ance, analog (High-Z). This is achieved by forcing the reset
state of all PRTxDM1 registers to FFh.
For additional information, refer to the
page
Bit 0: IOINT. This bit sets the GPIO Interrupt mode for all
pins in the CY8C20x34 PSoC devices. GPIO interrupts are
controlled at each pin by the PRTxIE registers, and also by
the global GPIO bit in the INT_MSK0 register.
For additional information, refer to the
page
DM1
0
0
1
1
Modes
Drive
183, and the
187.
DM0
Bit 3
Bit 3
0
1
0
1
Resistive pull up
Strong drive
High impedance,
analog ( reset state )
Open drain low
Pin State
Bit 2
Bit 2
PRTxDM1 register on page
PSoC CY8C20x34 TRM, Version 1.0
REG_EN
Bit 1
Bit 1
Resistive high, strong low
Strong high, strong low
High-Z high and low, digital input dis-
abled (for zero power) ( reset state )
High-Z high (digital input enabled),
strong low.
PRTxDM0 register on
IO_CFG register on
Description
IOINT
Bit 0
Bit 0
184.
RW : FF
Access
RW : 00
Access
RW : 00