MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 9

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

Burst Type
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
by the burst length, the burst type and the starting col-
umn address, as shown in Table 1.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
M12, M11, M10 = “0, 0, 0”
to ensure compatibility
with future devices.
*Should program
Accesses within a given burst may be programmed to
The ordering of accesses within a burst is determined
12
A12
Reserved*
11
A11
Mode Register Definition
10
A10
WB
M9
0
1
9
A9
Op Mode
8
A8
7
A7
Programmed Burst Length
M8
Figure 1
0
Single Location Access
-
CAS Latency
6
Write Burst Mode
A6
5
M7
A5
0
-
4
A4
M3
BT
Defined
0
1
M6-M0
3
A3
-
M2
M6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
2
A2
M1
M5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
0
A0
Full Page
Reserved
Reserved
Reserved
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8
9
NOTE: 1. For full-page accesses: y = 4,096 (x4); y = 2,048
Length
Burst
Page
Full
(y)
2
4
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2. For a burst length of two, A1-A9, A11, A12 (x4);
3. For a burst length of four, A2-A9, A11, A12 (x4);
4. For a burst length of eight, A3-A9, A11, A12 (x4);
5. For a full-page burst, the full row is selected and
6. Whenever a boundary of the block is reached
7. For a burst length of one, A0-A9, A11, A12 (x4);
Starting Column
(x8); y = 1,024 (x16).
A1-A9, A11 (x8); or A1-A9 (x16) select the block-
of-two burst; A0 selects the starting column
within the block.
A2-A9, A11 (x8); or A2-A9 (x16) select the block-
of-four burst; A0-A1 select the starting column
within the block.
A3-A9, A11 (x8); or A3-A9 (x16) select the block-
of-eight burst; A0-A2 select the starting column
within the block.
A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9
(x16) select the starting column.
within a given sequence above, the following
access wraps within the block.
A0-A9, A11 (x8); or A0-A9 (x16) select the unique
column to be accessed, and Mode Register bit M3
is ignored.
n = A0-A11/9/8
A2 A1 A0
(location 0-y)
0
0
0
0
1
1
1
1
Address
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
Burst Definition
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
512Mb: x4, x8, x16
Table 1
Cn, Cn + 1, Cn + 2
Type = Sequential
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn + 3, Cn + 4...
Order of Accesses Within a Burst
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn…
0-1
1-0
©2000, Micron Technology, Inc.
Type = Interleaved
Not Supported
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
SDRAM
ADVANCE
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0