MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 44

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

DQML, DQMH
TIMING PARAMETERS
NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
*CAS latency indicated in parentheses.
SYMBOL*
t
t
t
t
t
t
t
t
t
t
COMMAND
A0-A9, A11
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
BA0, BA1
DQM/
CKE
CLK
A10
DQ
2. x16: A11 and A12 = “Don’t Care”
3. READ command not allowed else
x8: A12 = “Don’t Care”
t CKS
t CMS
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CMH
t CKH
t AH
t AH
t AH
t RCD
t RAS
t RC
MIN
t CK
0.8
1.5
2.5
2.5
7.5
0.8
1.5
7
T1
-7E
NOP
MAX
5.4
5.4
SINGLE READ – WITH AUTO PRECHARGE
t CL
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
10
T2
NOP 3
t CH
-75
t
RAS would be violated
MAX
5.4
6
UNITS
T3
NOP 3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ENABLE AUTO PRECHARGE
t CMS
44
COLUMN m 2
BANK
T4
READ
t CMH
CAS Latency
SYMBOL*
t
t
t
t
t
t
t
t
t
t
CMH
CMS
HZ (3)
HZ (2)
LZ
OH
RAS
RC
RCD
RP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
NOP
t AC
t RP
D
T6
OUT
NOP
t OH
512Mb: x4, x8, x16
MIN
m
t HZ
0.8
1.5
2.7
37
60
15
15
1
1
-7E
120,000
MAX
5.4
5.4
ACTIVE
ROW
BANK
T7
ROW
MIN
0.8
1.5
2.7
44
66
20
20
1
©2000, Micron Technology, Inc.
-75
120,000
SDRAM
ADVANCE
MAX
5.4
T8
6
NOP
DON’T CARE
UNDEFINED
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns