MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 19

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Figure 11 for each possible CAS latency; data
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
A fixed-length READ burst may be followed by, or
COMMAND
COMMAND
NOTE: DQM is LOW.
ADDRESS
ADDRESS
CLK
CLK
DQ
DQ
BANK a,
BANK a,
COL n
COL n
T0
T0
READ
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
NOP
NOP
READ to PRECHARGE
T2
T2
NOP
NOP
D
OUT
n
Figure 11
T3
T3
19
NOP
NOP
n + 1
D
D
OUT
OUT
n
element n + 3 is either the last of a burst of four or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until
precharge time is hidden during the access of the last
data element(s).
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same op-
PRECHARGE
PRECHARGE
In the case of a fixed-length burst being executed to
(a or all)
(a or all)
BANK
BANK
T4
T4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X = 1 cycle
n + 2
D
n + 1
D
OUT
OUT
X = 2 cycles
T5
T5
NOP
NOP
n + 2
n + 3
D
D
OUT
OUT
t RP
t RP
t
RP is met. Note that part of the row
512Mb: x4, x8, x16
T6
T6
NOP
NOP
n + 3
D
OUT
DON’T CARE
BANK a,
BANK a,
ACTIVE
ACTIVE
T7
T7
ROW
ROW
©2000, Micron Technology, Inc.
SDRAM
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