MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 29

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

NOTE (continued):
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
11. Does not affect the state of the bank and acts as a NOP to that bank.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
must be applied on each positive clock edge during these states.
READs or WRITEs with auto precharge disabled.
Accessing Mode
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
Register: Starts with registration of a LOAD MODE REGISTER command and ends when
the SDRAM will be in the all banks idle state.
Once
all banks will be in the idle state.
t
MRD is met, the SDRAM will be in the all banks idle state.
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16
t
t
RP is met. Once
RC is met. Once
t
MRD has been met.
©2000, Micron Technology, Inc.
SDRAM
ADVANCE
t
t
RP is met,
RC is met,