MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 37

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
SYMBOL*
t
t
t
t
t
AH
AS
CH
CL
CK (3)
A0-A9, A11, A12
DQML, DQMH
COMMAND
Precharge all
BA0, BA1
active banks
DQM/
CLK
CKE
A10
DQ
High-Z
t CMS
t CKS
t AS
SINGLE BANK
PRECHARGE
ALL BANKS
BANK(S)
T0
MIN
t CMH
t CKH
0.8
1.5
2.5
2.5
t AH
7
-7E
Two clock cycles
MAX
All banks idle, enter
power-down mode
t CK
T1
NOP
MIN
0.8
1.5
2.5
2.5
7.5
-75
MAX
POWER-DOWN MODE
t CKS
t CL
T2
UNITS
NOP
ns
ns
ns
ns
ns
t CH
Input buffers gated off while in
power-down mode
37
Exit power-down mode
SYMBOL*
t
t
t
t
t
CK (2)
CKH
CKS
CMH
CMS
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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1
t CKS
512Mb: x4, x8, x16
MIN
7.5
0.8
1.5
0.8
1.5
Tn + 1
NOP
All banks idle
-7E
MAX
MIN
0.8
1.5
0.8
1.5
10
Tn + 2
ACTIVE
©2000, Micron Technology, Inc.
-75
ROW
ROW
BANK
SDRAM
ADVANCE
DON’T CARE
MAX
UNITS
ns
ns
ns
ns
ns