MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 22

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

subsequent READ command, and data for a fixed-length
WRITE burst may be immediately followed by a READ
command. Once the READ command is registered, the
data inputs will be ignored, and WRITEs will not be
executed. An example is shown in Figure 17. Data n + 1 is
either the last of a burst of two or the last desired of a
longer burst.
by, or truncated with, a PRECHARGE command to the
same bank (provided that auto precharge was not acti-
vated), and a full-page WRITE burst may be truncated
with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued
clock edge at which the last desired input data element is
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
COMMAND
COMMAND
ADDRESS
ADDRESS
Data for any WRITE burst may be truncated with a
Data for a fixed-length WRITE burst may be followed
NOTE:
NOTE:
CLK
DQ
CLK
DQ
The WRITE command may be to any bank, and the READ command
may be to any bank. DQM is LOW. CAS latency = 2 for illustration.
WRITE
BANK,
COL n
D
T0
Random WRITE Cycles
n
IN
Each WRITE command may be to any bank.
DQM is LOW.
BANK,
WRITE
COL n
D
T0
n
IN
WRITE To READ
n + 1
NOP
D
T1
IN
Figure 16
Figure 17
WRITE
BANK,
COL a
T1
D
a
IN
BANK,
READ
COL b
T2
WRITE
BANK,
COL x
T2
D
T3
x
NOP
IN
NOP
D
T4
WRITE
BANK,
COL m
OUT
b
T3
t
D
WR after the
m
IN
NOP
T5
b + 1
D
OUT
22
registered. The auto precharge mode requires a
least one clock plus time, regardless of frequency. In
addition, when truncating a WRITE burst, the DQM sig-
nal must be used to mask input data for the clock edge
prior to, and the clock edge coincident with, the
PRECHARGE command. An example is shown in Figure
18. Data n + 1 is either the last of a burst of two or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until
issued coincident with the first coincident clock edge (T2
in Figure 18) on an A1 Version and with the second clock
on an A2 Version (Figure 18.)
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same op-
eration that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropriate
time to issue the command; the advantage of the
COMMAND
COMMAND
t WR @ t CLK ≥ 15ns
t WR = t CLK < 15ns
NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
ADDRESS
ADDRESS
In the case of a fixed-length burst being executed to
DQM
DQM
CLK
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK a,
BANK a,
WRITE
WRITE
COL n
COL n
D
D
T0
n
n
IN
IN
WRITE To PRECHARGE
n + 1
n + 1
NOP
NOP
T1
D
D
IN
IN
t
Figure 18
WR
512Mb: x4, x8, x16
PRECHARGE
t
(a or all)
RP is met. The precharge can be
BANK
NOP
T2
t
WR
PRECHARGE
(a or all)
BANK
T3
NOP
t RP
NOP
NOP
T4
©2000, Micron Technology, Inc.
t RP
SDRAM
ADVANCE
BANK a,
ACTIVE
ROW
NOP
T5
DON’T CARE
t
WR of at
BANK a,
ACTIVE
ROW
T6
NOP