MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 18

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

subsequent WRITE command, and data from a fixed-
length READ burst may be immediately followed by data
from a WRITE command (subject to bus turnaround
limitations). The WRITE burst may be initiated on the
clock edge immediately following the last (or last de-
sired) data element from the READ burst, provided that I/
O contention can be avoided. In a given system design,
there may be a possibility that the device driving the
input data will go Low-Z before the SDRAM DQs go High-
Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
shown in Figures 9 and 10. The DQM signal must be
asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers)
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
Data from any READ burst may be truncated with a
The DQM input is used to avoid I/O contention, as
COMMAND
ADDRESS
NOTE:
DQM
CLK
DQ
A CAS latency of three is used for illustration. The READ
command may be to any bank, and the WRITE command
may be to any bank. If a burst of one is used, then DQM is
not required.
T0
BANK,
COL n
READ
READ to WRITE
T1
Figure 9
NOP
T2
NOP
T3
NOP
D
t HZ
OUT
t CK
n
T4
BANK,
WRITE
COL b
D
IN
b
t
DS
18
to suppress data-out from the READ. Once the WRITE
command is registered, the DQs will go High-Z (or re-
main High-Z), regardless of the state of the DQM signal;
provided the DQM was active on the clock just prior to
the WRITE command that truncated the READ com-
mand. If not, the second WRITE will be an invalid WRITE.
For example, if DQM was LOW during T4 in Figure 10,
then the WRITEs at T5 and T7 would be valid, while the
WRITE at T6 would be invalid.
WRITE command (DQM latency is zero clocks for input
buffers) to ensure that the written data is not masked.
Figure 9 shows the case where the clock frequency allows
for bus contention to be avoided without adding a NOP
cycle, and Figure 10 shows the case where the additional
NOP is needed.
COMMAND
READ to WRITE with Extra Clock Cycle
ADDRESS
The DQM signal must be de-asserted prior to the
NOTE:
DQM
CLK
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.
BANK,
COL n
T0
READ
T1
NOP
Figure 10
512Mb: x4, x8, x16
T2
NOP
T3
NOP
t HZ
D
OUT
n
©2000, Micron Technology, Inc.
T4
NOP
SDRAM
ADVANCE
DON’T CARE
T5
BANK,
COL b
WRITE
D
IN
b
t
DS