MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 12

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

COMMAND INHIBIT
mands from being executed by the SDRAM, regardless of
whether the CLK signal is enabled. The SDRAM is effec-
tively deselected. Operations already in progress are not
affected.
NO OPERATION (NOP)
form a NOP to an SDRAM which is selected (CS# is LOW).
This prevents unwanted commands from being regis-
tered during idle or wait states. Operations already in
progress are not affected.
LOAD MODE REGISTER
should be driven LOW.) See Mode Register heading in the
Register Definition section. The LOAD MODE REGISTER
command can only be issued when all banks are idle, and
a subsequent executable command cannot be issued
until
ACTIVE
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A12 selects the row. This
row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening a
different row in the same bank.
READ
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-
A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) selects
the starting column location. The value on input A10
determines whether or not auto precharge is used. If auto
precharge is selected, the row being accessed will be
precharged at the end of the READ burst; if auto precharge
is not selected, the row will remain open for subsequent
accesses. Read data appears on the DQs subject to the
logic level on the DQM inputs two clocks earlier. If a given
DQM signal was registered HIGH, the corresponding
DQs will be High-Z two clocks later; if the DQM signal was
registered LOW, the DQs will provide valid data.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
The COMMAND INHIBIT function prevents new com-
The NO OPERATION (NOP) command is used to per-
The Mode Register is loaded via inputs A0-A11 (A12
The ACTIVE command is used to open (or activate) a
The READ command is used to initiate a burst read
t
MRD is met.
12
WRITE
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-
A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) selects
the starting column location. The value on input A10
determines whether or not auto precharge is used. If auto
precharge is selected, the row being accessed will be
precharged at the end of the WRITE burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses. Input data appearing on the DQs is
written to the memory array subject to the DQM input
logic level appearing coincident with the data. If a given
DQM signal is registered LOW, the corresponding data
will be written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that byte/column
location.
PRECHARGE
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specified time (
issued. Input A10 determines whether one or all banks
are to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands
being issued to that bank.
AUTO PRECHARGE
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accom-
plished by using A10 to enable auto precharge in con-
junction with a specific READ or WRITE command. A
PRECHARGE of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst, except in
the full-page burst mode, where auto precharge does not
apply. Auto precharge is nonpersistent in that it is either
enabled or disabled for each individual READ or WRITE
command.
at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the
precharge time (
if an explicit PRECHARGE command was issued at the
earliest possible time, as described for each burst type in
the Operation section of this data sheet.
The WRITE command is used to initiate a burst write
The PRECHARGE command is used to deactivate the
Auto precharge is a feature which performs the same
Auto precharge ensures that the precharge is initiated
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
RP) is completed. This is determined as
RP) after the PRECHARGE command is
512Mb: x4, x8, x16
©2000, Micron Technology, Inc.
SDRAM
ADVANCE