MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 28

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TRUTH TABLE 3 – CURRENT STATE BANK n - COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
NOTE: 1. This table applies when CKE
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
CURRENT STATE CS# RAS# CAS# WE#
Row Active
Precharge
Precharge
Disabled)
Disabled)
(Auto
(Auto
Write
Read
Any
Idle
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
met (if the previous state was self refresh).
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to
Truth Table 4.
Row Activating: Starts with registration of an ACTIVE command and ends when
Write w/Auto
Read w/Auto
Precharging: Starts with registration of a PRECHARGE command and ends when
Row Active: A row in the bank has been activated, and
Precharge
Precharge
Enabled: Starts with registration of a READ command with auto precharge enabled and ends when
Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Idle: The bank has been precharged, and
H
H
H
H
H
H
H
H
H
register accesses are in progress.
terminated.
terminated.
bank will be in the idle state.
bank will be in the row active state.
been met. Once
been met. Once
X
L
L
L
L
L
L
L
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
n-1
H
H
H
H
H
H
was HIGH and CKE
X
L
L
L
L
L
L
L
L
L
L
t
t
RP is met, the bank will be in the idle state.
RP is met, the bank will be in the idle state.
COMMAND (ACTION)
AUTO REFRESH
WRITE (Select column and start WRITE burst)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
n
is HIGH (see Truth Table 2) and after
28
t
RP has been met.
t
RCD has been met. No data bursts/accesses and no
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
512Mb: x4, x8, x16
RCD is met. Once
t
RP is met. Once
t
XSR has been
t
©2000, Micron Technology, Inc.
RCD is met, the
t
RP is met, the
SDRAM
ADVANCE
t
RP has
t
RP has
NOTES
10
10
10
10
10
10
11
7
7
8
8
9
8
9