MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 45

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
A0-A9, A11, A12
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
COMMAND
BA0, BA1
DQM/
2. x16: A11 and A12 = “Don’t Care”
CLK
A10
CKE
DQ
x8: A12 = “Don’t Care”
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
BANK 0
T0
ROW
ROW
t CKH
t CMH
t AH
t AH
t AH
t RCD - BANK 0
t RAS - BANK 0
t
t
RC - BANK 0
RRD
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
7
t CK
-7E
T1
NOP
MAX
5.4
5.4
ALTERNATING BANK READ ACCESSES
ENABLE AUTO PRECHARGE
t CMS
t CL
MIN
COLUMN m 2
0.8
1.5
2.5
2.5
7.5
0.8
1.5
10
BANK 0
T2
READ
-75
t CMH
t CH
MAX
CAS Latency - BANK 0
5.4
6
UNITS
T3
NOP
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t LZ
t AC
45
BANK 3
ACTIVE
T4
ROW
ROW
D
OUT
t OH
t AC
SYMBOL*
t
t
t
t
t
t
t
t
t
m
CMH
CMS
LZ
OH
RAS
RC
RCD
RP
RRD
t RCD - BANK 1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
T5
OUT
NOP
m + 1
t OH
t AC
ENABLE AUTO PRECHARGE
COLUMN b 2
BANK 3
D
T6
OUT
READ
512Mb: x4, x8, x16
1
MIN
m + 2
t OH
0.8
1.5
2.7
37
60
15
15
14
1
t AC
CAS Latency - BANK 1
-7E
120,000
MAX
t RP - BANK 0
D
T7
OUT
NOP
m + 3
t OH
t AC
MIN
0.8
1.5
2.7
44
66
20
20
15
1
©2000, Micron Technology, Inc.
-75
120,000
SDRAM
ADVANCE
MAX
BANK 0
T8
ACTIVE
ROW
ROW
DON’T CARE
UNDEFINED
D
OUT
t RCD - BANK 0
t OH
t AC
b
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns