MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 48

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
A0-A9, A11, A12
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
CMH
COMMAND
BA0, BA1
DQM/
2. 14ns to 15ns is required between <D
3. x16: A11 and A12 = “Don’t Care”
CKE
A10
CLK
DQ
x8: A12 = “Don’t Care”
t CKS
t CMS
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
7
T1
NOP
-7E
MAX
DISABLE AUTO PRECHARGE
t CMS
WRITE – WITHOUT AUTO PRECHARGE
t CL
t DS
COLUMN m 3
WRITE
T2
BANK
D
MIN
IN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
t CMH
10
t CH
t DH
m
-75
MAX
IN
t DS
D
m> and the PRECHARGE command, regardless of frequency.
IN
T3
NOP
m + 1
t DH
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
t DS
D
IN
T4
NOP
m + 2
48
t DH
SYMBOL*
t
t
t
t
t
t
t
t
t DS
CMS
DH
DS
RAS
RC
RCD
RP
WR
D
IN
NOP
T5
m + 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DH
t
WR
T6
NOP
2
1
512Mb: x4, x8, x16
PRECHARGE
MIN
SINGLE BANK
ALL BANKs
1.5
0.8
1.5
37
60
15
15
14
T7
BANK
-7E
120,000
MAX
t RP
NOP
T8
MIN
1.5
0.8
1.5
44
66
20
20
15
DON’T CARE
©2000, Micron Technology, Inc.
-75
120,000
SDRAM
ADVANCE
MAX
ACTIVE
ROW
ROW
BANK
T9
UNITS
ns
ns
ns
ns
ns
ns
ns
ns