MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 36

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
A0-A9, A11, A12
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CKH
COMMAND
BA0, BA1
DQM/
2. If CS is HIGH at clock high time, all commands applied are NOP, with CKE a “Don’t Care.”
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at
CKE
A10
DQ
CK
T = 100µs
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Power-up:
V
CLK stable
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MIN
DD
and
t CKS
t CMS
T0
NOP
t CKH
High-Z
t CMH
MIN
0.8
1.5
2.5
2.5
7.5
0.8
7
-7E
SINGLE BANK
t CMS
ALL BANKS
t CK
MAX
PRECHARGE
INITIALIZE AND LOAD MODE REGISTER
BANKS
T1
ALL
t
t CMH
t RP
P + 1.
Precharge
all banks
MIN
0.8
1.5
2.5
2.5
7.5
0.8
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10
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t CMS
-75
Tn + 1
REFRESH
AUTO
MAX
t CMH
t CH
AUTO REFRESH
t RFC
UNITS
ns
ns
ns
ns
ns
ns
ns
NOP
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NOP
36
t CL
To + 1
REFRESH
SYMBOL*
t
t
t
t
t
t
AUTO
CKS
CMH
CMS
MRD
RFC
RP
AUTO REFRESH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
t RFC
NOP
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NOP
t AS
t AS
LOAD MODE
Tp + 1
512Mb: x4, x8, x16
REGISTER
MIN
1.5
0.8
1.5
66
15
2
CODE
CODE
2
t AH
t AH
Program Mode Register
-7E
5
MAX
t MRD
Tp + 2
NOP
MIN
1.5
0.8
1.5
66
20
2
©2000, Micron Technology, Inc.
-75
SDRAM
ADVANCE
MAX
1, 3, 4
Tp + 3
ACTIVE
BANK
ROW
ROW
DON’T CARE
UNDEFINED
UNITS
t
ns
ns
ns
CK
ns
ns