MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 52

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

A0-A9, A11, A12
TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
CMH
COMMAND
BA0, BA1
DQM/
2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. x16: A11 and A12 = “Don’t Care”
CLK
CKE
A10
DQ
x8: A12 = “Don’t Care”
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
BANK 0
T0
ROW
ROW
t CKH
t CMH
t AH
t AH
t AH
t RCD - BANK 0
t RAS - BANK 0
t
t
RC - BANK 0
RRD
t CK
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
7
T1
NOP
-7E
MAX
ENABLE AUTO PRECHARGE
ALTERNATING BANK WRITE ACCESSES
t CMS
t CL
t DS
COLUMN m 3
BANK 0
WRITE
T2
D
MIN
IN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
10
t CMH
t CH
t DH
m
-75
MAX
t DS
D
IN
T3
NOP
m + 1
t DH
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
t DS
D
ACTIVE
BANK 1
IN
T4
ROW
ROW
m + 2
52
t DH
t RCD - BANK 1
SYMBOL*
t
t
t
t
t
t
t
t
t
t DS
CMS
DH
DS
RAS
RC
RCD
RP
RRD
WR
D
IN
T5
NOP
m + 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DH
t WR - BANK 0
ENABLE AUTO PRECHARGE
COLUMN b 3
t DS
BANK 1
WRITE
T6
D
IN
t DH
b
Note 2
512Mb: x4, x8, x16
t DS
MIN
1
1.5
0.8
1.5
D
37
60
15
15
14
NOP
IN
T7
b + 1
-7E
t DH
120,000
MAX
t DS
t RP - BANK 0
D
IN
NOP
T8
Note 2
b + 2
MIN
1.5
0.8
1.5
t DH
44
66
20
20
15
©2000, Micron Technology, Inc.
-75
120,000
SDRAM
ADVANCE
MAX
t DS
D
BANK 0
ACTIVE
T9
ROW
IN
ROW
b + 3
t
t
RCD - BANK 0
WR - BANK 1
DON’T CARE
t DH
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns