MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 40

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTES: 1. No maximum time limit for Self Refresh.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
A0-A9, A11,A12
DQML, DQMH
SYMBOL*
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CKH
COMMAND
BA0, BA1
2.
DQM/
CKE
A10
CLK
t
DQ
XSR requires minimum of two clocks regardless of frequency or timing.
High-Z
Precharge all
t CKS
active banks
t CMS
t
SINGLE BANK
AS
PRECHARGE
ALL BANKS
BANK(S)
T0
t CKH
t CMH
t
AH
t CK
MIN
0.8
1.5
2.5
2.5
7.5
0.8
7
-7E
MAX
t RP
T1
NOP
t CH
MIN
0.8
1.5
2.5
2.5
7.5
0.8
10
Enter self refresh mode
-75
MAX
t CKS
t CL
SELF REFRESH MODE
REFRESH
AUTO
CLK stable prior to exiting
t
T2
RAS(MAX) applies to non-Self Refresh mode.
UNITS
ns
ns
ns
ns
ns
ns
ns
self refresh mode
≥
t RAS(MIN)
(
(
(
(
(
(
)
)
(
(
)
(
)
(
(
)
(
)
(
)
)
)
)
)
)
)
(
(
(
(
(
(
(
)
)
(
(
)
)
)
(
(
(
(
(
)
)
)
)
(
(
)
)
)
)
)
)
)
(
(
40
)
(
)
)
1
SYMBOL*
t
t
t
t
t
t
CKS
CMH
CMS
RAS
RP
XSR
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(Restart refresh time base)
Exit self refresh mode
Tn + 1
t XSR
NOP
(
(
(
(
(
(
(
(
)
(
)
(
(
)
(
)
(
)
(
)
)
)
)
(
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
(
)
)
or COMMAND
512Mb: x4, x8, x16
MIN
1.5
0.8
1.5
37
15
67
INHIBIT
To + 1
-7E
120,000
MAX
MIN
1.5
0.8
1.5
44
20
75
©2000, Micron Technology, Inc.
To + 2
REFRESH
-75
AUTO
120,000
SDRAM
ADVANCE
MAX
DON’T CARE
UNITS
ns
ns
ns
ns
ns
ns