MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet

MT48LC128M4A2TG

Manufacturer Part Number

MT48LC128M4A2TG

Description

SYNCHRONOUS DRAM

Manufacturer

MICRON [Micron Technology]

Datasheet

1.MT48LC128M4A2TG.pdf (55 pages)

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‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE

BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

SYNCHRONOUS

DRAM

FEATURES

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive

• Internal pipelined operation; column address can be

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto Precharge, includes CONCURRENT AUTO

• Self Refresh Mode

• 64ms, 8,192-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

OPTIONS

• Configurations

• WRITE Recovery (

• Plastic Package – OCPL

• Timing (Cycle Time)

• Self Refresh

• Operating Temperature

NOTE: 1. Refer to Micron Technical Note TN-48-05.

512Mb SDRAM PART NUMBERS

512Mb: x4, x8, x16 SDRAM

512MSDRAM_D.p65 – Rev. D; Pub 1/02

PART NUMBER

MT48LC128M4A2TG

MT48LC64M8A2TG

MT48LC32M16A2TG

edge of system clock

changed every clock cycle

PRECHARGE, and Auto Refresh Modes

128 Meg x 4 (32 Meg x 4 x 4 banks)

54-pin TSOP II (400 mil)

7.5ns @ CL = 2 (PC133)

7.5ns @ CL = 3 (PC133)

Standard

Low power

Commercial (0

WR = “2 CLK”

64 Meg x 8 (16 Meg x 8 x 4 banks)

32 Meg x 16 (8 Meg x 16 x 4 banks)

2. Off-center parting line.

MT48LC32M16A2TG-75

C to +70

Part Number Example:

WR)

ARCHITECTURE

128 Meg x 4

64 Meg x 8

32 Meg x 16

MARKING

128M4

32M16

64M8

None

-7E

-75

MT48LC128M4A2 – 32 Meg x 4 x 4 banks

MT48LC64M8A2 – 16 Meg x 8 x 4 banks

MT48LC32M16A2 – 8 Meg x 16 x 4 banks

For the latest data sheet, please refer to the Micron Web site:

www.micron.com/dramds

KEY TIMING PARAMETERS

*CL = CAS (READ) latency

NOTE: The # symbol indicates signal is active LOW. A dash

GRADE FREQUENCY CL = 2* CL = 3*

Configuration

Refresh Count

Row Addressing

Bank Addressing

Column Addressing 4K (A0–A9, A11, A12)

SPEED

DQ0

DQ1

-7E

-75

-7E

-75

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DQ0

DQ1

DQ2

DQ3

(–) indicates x8 and x4 pin function is same as x16

pin function.

Pin Assignment (Top View)

DQML

CAS#

RAS#

x16

VssQ

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

WE#

BA0

BA1

A10

143 MHz

133 MHz

100 MHz

CS#

CLOCK

32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks

128 Meg x 4

4 (BA0, BA1)

8K (A0–A12)

54-Pin TSOP

512Mb: x4, x8, x16

ACCESS TIME

5.4ns

6ns

–

2K (A0–A9, A11)

64 Meg x 8

8K (A0–A12)

4 (BA0, BA1)

5.4ns

–

SETUP

TIME

1.5ns

ADVANCE

x16

Vss

DQ15

VssQ

DQ14

DQ13

DQ12

DQ11

VssQ

DQ10

DQ9

DQ8

Vss

DQMH

CLK

CKE

A12

A11

Vss

SDRAM

32 Meg x 16

8K (A0–A12)

4 (BA0, BA1)

1K (A0–A9)

DQ7

DQ6

DQ5

DQ4

DQM

HOLD

TIME

0.8ns

DQ3

DQ2

DQM

‡

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