MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 13

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

BURST TERMINATE
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet.
AUTO REFRESH
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required. All active banks must be PRECHARGED prior
to issuing a AUTO REFRESH comand. The AUTO RE-
FRESH command should not be issued until the mini-
mum tRP has been met after the PRECHARGE command
as shown in the operations section.
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 512Mb SDRAM
requires 8,192 AUTO REFRESH cycles every 64ms (
regardless of width option. Providing a distributed AUTO
REFRESH command every 7.81µs will meet the refresh
requirement and ensure that each row is refreshed. Alter-
natively, 8,192 AUTO REFRESH commands can be issued
in a burst at the minimum cycle rate (
64ms.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
The BURST TERMINATE command is used to trun-
AUTO REFRESH is used during normal operation of
The addressing is generated by the internal refresh
t
RC), once every
t
REF),
13
SELF REFRESH
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the SDRAM
retains data without external clocking. The SELF RE-
FRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). Once the SELF
REFRESH command is registered, all the inputs to the
SDRAM become “Don’t Care” with the exception of CKE,
which must remain LOW.
vides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to
and may remain in self refresh mode for an indefinite
period beyond that.
quence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing con-
straints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
t
internal refresh in progress.
commands must be issued every 7.81µs or less as both
SELF REFRESH and AUTO REFRESH utilize the row re-
fresh counter.
XSR because time is required for the completion of any
The SELF REFRESH command can be used to retain
Once self refresh mode is engaged, the SDRAM pro-
The procedure for exiting self refresh requires a se-
Upon exiting the self refresh mode, AUTO REFRESH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16
©2000, Micron Technology, Inc.
SDRAM
ADVANCE
t
RAS