MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 21

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

WRITEs
as shown in Figure 13.
with the WRITE command, and auto precharge is either
enabled or disabled for that access. If auto precharge is
enabled, the row being accessed is precharged at the
completion of the burst. For the generic WRITE com-
mands used in the following illustrations, auto precharge
is disabled.
will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each
successive positive clock edge. Upon completion of a
fixed-length burst, assuming no other commands have
been initiated, the DQs will remain High-Z and any addi-
tional input data will be ignored (see Figure 14). A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to the start address and continue.)
subsequent WRITE command, and data for a fixed-length
WRITE burst may be immediately followed by data for a
WRITE command. The new WRITE command can be
issued on any clock following the previous WRITE com-
mand, and the data provided coincident with the new
command applies to the new command. An example is
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
WRITE bursts are initiated with a WRITE command,
The starting column and bank addresses are provided
During WRITE bursts, the first valid data-in element
Data for any WRITE burst may be truncated with a
A0-A9, A11, A12: x4
A9, A11, A12: x16
A0-A9, A11: x8
A11, A12: x8
BA0, BA, 1
A0-A9: x16
A12: x4
CAS#
RAS#
WE#
A10
WRITE Command
CKE
CLK
CS#
Figure 13
HIGH
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
COLUMN
ADDRESS
ADDRESS
BANK
21
shown in Figure 15. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. The 512Mb
SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch archi-
tecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed
random write accesses within a page can be performed to
the same bank, as shown in Figure 16, or each subsequent
WRITE may be performed to a different bank.
COMMAND
ADDRESS
COMMAND
NOTE B
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ADDRESS
CLK
DQ
NOTE:
CLK
DQ
t l
WRITE
BANK,
WRITE to WRITE
COL n
T0
D
n
IN
WRITE Burst
DQM is LOW. Each WRITE
command may be to any bank.
WRITE
th 2 DQM i LOW
BANK,
COL n
Figure 14
Figure 15
D
T0
n
512Mb: x4, x8, x16
IN
NOP
n + 1
T1
D
IN
n + 1
NOP
D
T1
IN
NOP
T2
DON’T CARE
©2000, Micron Technology, Inc.
WRITE
BANK,
SDRAM
COL b
ADVANCE
T2
D
b
IN
T3
NOP