MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 15

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

READs
shown in Figure 5.
with the READ command, and auto precharge is either
enabled or disabled for that burst access. If auto precharge
is enabled, the row being accessed is precharged at the
completion of the burst. For the generic READ com-
mands used in the following illustrations, auto precharge
is disabled.
the starting column address will be available following
the CAS latency after the READ command. Each subse-
quent data-out element will be valid by the next positive
clock edge. Figure 6 shows general timing for each pos-
sible CAS latency setting.
A0-A9, A11, A12: x4
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
A9, A11, A12: x16
READ bursts are initiated with a READ command, as
The starting column and bank addresses are provided
During READ bursts, the valid data-out element from
A0-A9, A11: x8
A11, A12: x8
A0-A9: x16
A12: x4
BA0,1
CAS#
RAS#
WE#
A10
CLK
CKE
CS#
READ Command
HIGH
Figure 5
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
COLUMN
ADDRESS
ADDRESS
BANK
15
mands have been initiated, the DQs will go High-Z. A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to the start address and continue.)
subsequent READ command, and data from a fixed-length
READ burst may be immediately followed by data from a
READ command. In either case, a continuous flow of data
can be maintained. The first data element from the new
burst follows either the last element of a completed burst
or the last desired data element of a longer burst that is
being truncated. The new READ command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one. This is shown in Figure 7 for CAS
COMMAND
COMMAND
Upon completion of a burst, assuming no other com-
Data from any READ burst may be truncated with a
CLK
CLK
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
READ
READ
T0
T0
CAS Latency = 2
CAS Latency
Figure 6
NOP
NOP
512Mb: x4, x8, x16
T1
T1
t
t AC
LZ
CAS Latency = 3
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
©2000, Micron Technology, Inc.
SDRAM
ADVANCE
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4